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    Methods and apparatus for floorplanning and routing co-design
    1.
    发明授权
    Methods and apparatus for floorplanning and routing co-design 有权
    布局规划和路由协同设计的方法和设备

    公开(公告)号：US08863062B2

    公开(公告)日：2014-10-14

    申请号：US13544009

    申请日：2012-07-09

    申请人： Yi-Lin Chuang ,  Ji-Jan Chen ,  Ching-Fang Chen ,  Yun-Han Lee

    发明人： Yi-Lin Chuang ,  Ji-Jan Chen ,  Ching-Fang Chen ,  Yun-Han Lee

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  G06F17/5077 ,  G06F2217/40

    摘要： Methods and apparatus of performing floorplanning and routing for function blocks within a die and among multiple die are disclosed. Multiple die together with function blocks within each die may be represented by a flexible hierarchical (FH) tree. An initial floorplan for multiple die may be generated and hot spots between die or among function blocks within a die may be identified. Spacer blocks may be inserted between die, and block inflation may be performed, to remove hot spots. More perturbation of the block positions can be performed on the FH tree to rearrange the blocks and die. After the multiple die floorplanning, a plurality of micro bumps may be mapped to a plurality of pins of blocks of the plurality of die, placement and routing may be performed for the plurality of blocks within each die and connections for the plurality of dies.

    摘要翻译： 公开了对模具内和多个模具中的功能块执行布局规划和布线的方法和装置。 每个管芯中的多个管芯与功能块一起可以由柔性分层（FH）树表示。 可以产生多个管芯的初始平面图，并且可以识别管芯内的管芯之间的热点或管芯内的功能块之间的热点。 间隔块可以插入管芯之间，并且可以执行块膨胀以去除热点。 可以在FH树上执行更多的块位置的扰动，以重新排列块并死亡。 在多芯片布局图之后，可以将多个微凸块映射到多个芯片的块的多个引脚，可以针对每个管芯内的多个块执行放置和布线，并为多个管芯提供连接。

    Methods and Apparatus for Floorplanning and Routing Co-Design
    3.
    发明申请
    Methods and Apparatus for Floorplanning and Routing Co-Design 有权
    布局规划与路由协同设计方法与设备

    公开(公告)号：US20130290914A1

    公开(公告)日：2013-10-31

    申请号：US13544009

    申请日：2012-07-09

    申请人： Yi-Lin Chuang ,  Ji-Jan Chen ,  Ching-Fang Chen ,  Yun-Han Lee

    发明人： Yi-Lin Chuang ,  Ji-Jan Chen ,  Ching-Fang Chen ,  Yun-Han Lee

    IPC分类号： G06F17/50 ,  G06F9/455

    CPC分类号： G06F17/5072 ,  G06F17/5077 ,  G06F2217/40

    摘要： Methods and apparatus of performing floorplanning and routing for function blocks within a die and among multiple die are disclosed. Multiple die together with function blocks within each die may be represented by a flexible hierarchical (FH) tree. An initial floorplan for multiple die may be generated and hot spots between die or among function blocks within a die may be identified. Spacer blocks may be inserted between die, and block inflation may be performed, to remove hot spots. More perturbation of the block positions can be performed on the FH tree to rearrange the blocks and die. After the multiple die floorplanning, a plurality of micro bumps may be mapped to a plurality of pins of blocks of the plurality of die, placement and routing may be performed for the plurality of blocks within each die and connections for the plurality of dies.

    摘要翻译： 公开了对模具内和多个模具中的功能块执行布局规划和布线的方法和装置。 每个管芯中的多个管芯与功能块一起可以由柔性分层（FH）树表示。 可以产生多个管芯的初始平面图，并且可以识别管芯内的管芯之间的热点或管芯内的功能块之间的热点。 间隔块可以插入管芯之间，并且可以执行块膨胀以去除热点。 可以在FH树上执行更多的块位置的扰动，以重新排列块并死亡。 在多芯片布局图之后，可以将多个微凸块映射到多个芯片的块的多个引脚，可以针对每个管芯内的多个块执行放置和布线，并为多个管芯提供连接。

    GROUP BOUNDING BOX REGION-CONSTRAINED PLACEMENT FOR INTEGRATED CIRCUIT DESIGN
    5.
    发明申请
    GROUP BOUNDING BOX REGION-CONSTRAINED PLACEMENT FOR INTEGRATED CIRCUIT DESIGN 有权
    集成电路设计的组接线盒区域约束放置

    公开(公告)号：US20140075404A1

    公开(公告)日：2014-03-13

    申请号：US13613678

    申请日：2012-09-13

    申请人： Yi-Lin Chuang ,  Chun-Cheng Ku ,  Yun-Han Lee ,  Shao-Yu Wang ,  Wei-Pin Changchien ,  Chin-Chou Liu

    发明人： Yi-Lin Chuang ,  Chun-Cheng Ku ,  Yun-Han Lee ,  Shao-Yu Wang ,  Wei-Pin Changchien ,  Chin-Chou Liu

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072

    摘要： Among other things, one or more systems and techniques for defining a group bounding box for related cells of an integrated circuit, and generating a new layout for the integrated circuit comprising the group bounding box are provided herein. That is, one or more group bounding boxes are defined based upon positional values of related cells. Such group bounding boxes are placed within the new layout based upon a placement technique, such as an objective function that takes into account wire length, timing, and cell density, for example. The one or more group bounding boxes are sized or reshaped to reduce cell overlap within the new layout. In this way, the new layout comprises related cells, bound by one or more group bounding boxes, that are placed within the new layout according to a configuration that mitigates wire length and timing delay of the integrated circuit.

    摘要翻译： 除此之外，本文提供了一种或多种用于定义用于集成电路的相关单元的组边界框以及为包括组边界框的集成电路生成新布局的系统和技术。 也就是说，基于相关单元的位置值来定义一个或多个组边界框。 基于诸如考虑线长度，定时和单元密度的目标函数的放置技术，将这样的组边界框放置在新布局内。 一个或多个组边界框的大小或重新形状以减少新布局中的单元格重叠。 以这种方式，新布局包括根据减轻集成电路的线长度和定时延迟的配置放置在新布局内的由一个或多个组边界框绑定的相关单元。

    Group bounding box region-constrained placement for integrated circuit design
    6.
    发明授权
    Group bounding box region-constrained placement for integrated circuit design 有权
    集成电路设计的边界区域约束布局

    公开(公告)号：US08701070B2

    公开(公告)日：2014-04-15

    申请号：US13613678

    申请日：2012-09-13

    申请人： Yi-Lin Chuang ,  Chun-Cheng Ku ,  Yun-Han Lee ,  Shao-Yu Wang ,  Wei-Pin Changchien ,  Chin-Chou Liu

    发明人： Yi-Lin Chuang ,  Chun-Cheng Ku ,  Yun-Han Lee ,  Shao-Yu Wang ,  Wei-Pin Changchien ,  Chin-Chou Liu

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072

    摘要： Among other things, one or more systems and techniques for defining a group bounding box for related cells of an integrated circuit, and generating a new layout for the integrated circuit comprising the group bounding box are provided herein. That is, one or more group bounding boxes are defined based upon positional values of related cells. Such group bounding boxes are placed within the new layout based upon a placement technique, such as an objective function that takes into account wire length, timing, and cell density, for example. The one or more group bounding boxes are sized or reshaped to reduce cell overlap within the new layout. In this way, the new layout comprises related cells, bound by one or more group bounding boxes, that are placed within the new layout according to a configuration that mitigates wire length and timing delay of the integrated circuit.

    摘要翻译： 除此之外，本文提供了一种或多种用于定义用于集成电路的相关单元的组边界框并且为包括组边界框的集成电路生成新布局的系统和技术。 也就是说，基于相关单元的位置值来定义一个或多个组边界框。 基于诸如考虑线长度，定时和单元密度的目标函数的放置技术，将这样的组边界框放置在新布局内。 一个或多个组边界框的大小或重新形状以减少新布局中的单元格重叠。 以这种方式，新布局包括根据减轻集成电路的线长度和定时延迟的配置放置在新布局内的由一个或多个组边界框绑定的相关单元。

    Reducing voltage drops in power networks using unused spaces in integrated circuits
    9.
    发明授权
    Reducing voltage drops in power networks using unused spaces in integrated circuits 有权
    降低集成电路中未使用空间的电力网络中的电压降

    公开(公告)号：US08276110B2

    公开(公告)日：2012-09-25

    申请号：US12692184

    申请日：2010-01-22

    申请人： Dinesh Baviskar ,  Wen-Hao Chen ,  Chung-Sheng Yuan ,  Mark Shane Peng ,  Yun-Han Lee

    发明人： Dinesh Baviskar ,  Wen-Hao Chen ,  Chung-Sheng Yuan ,  Mark Shane Peng ,  Yun-Han Lee

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F2217/78

    摘要： A method of designing an integrated circuit includes providing an integrated circuit design including a power network. A voltage drop mitigation system is provided, which includes a power strap enhancer configured to automatically find a source node and a terminal node in the power network. A redundant strap for the power network using the voltage drop mitigation system is added, wherein the redundant strap interconnects the source node and the terminal node. After the step of adding the redundant strap, dummy patterns may be added.

    摘要翻译： 设计集成电路的方法包括提供包括电力网络的集成电路设计。 提供一种电压降缓解系统，其包括被配置为在电力网络中自动找到源节点和终端节点的电力带增强器。 添加了使用电压降缓解系统的用于电力网络的冗余带，其中冗余带将源节点和终端节点互连。 在添加冗余带的步骤之后，可以添加虚拟图案。

    Large circular sense molecule array
    10.
    发明授权
    Large circular sense molecule array 失效
    大圆环分子阵列

    公开(公告)号：US07297520B2

    公开(公告)日：2007-11-20

    申请号：US10627882

    申请日：2003-07-25

    申请人： Jong-Gu Park ,  Yun-Han Lee

    发明人： Jong-Gu Park ,  Yun-Han Lee

    IPC分类号： C12N15/66

    CPC分类号： C12Q1/6837 ,  C12Q2565/519 ,  C12Q2525/307

    摘要： Large circular (LC)-sense molecules in an array is disclosed. The LC-sense molecules array is combined with cDNA hybridization to detect differences in expression profile between different cells. LC-sense molecules were purified from nonredundant clones with recombinant phagemid and arrayed onto silanized slide glasses. By hybridization of LC-sense array with Cy3 or Cy5-labelled cDNA preparations at 60° C., 29 up-regulated and 6 down-regulated genes in cancerous liver tissue were detected.

    摘要翻译： 公开了一种阵列中的大圆形（LC）感应分子。 将LC检测分子阵列与cDNA杂交组合以检测不同细胞之间的表达谱的差异。 用重组噬菌粒从非冗余克隆纯化LC-有义分子，并将其排列到硅烷化载玻片上。 通过LC-sense阵列与Cy3或Cy5标记的cDNA制备物在60℃杂交，检测到癌肝组织中的29个上调基因和6个下调基因。