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    System and Method for Configurable Multi-standard Receiver
    1.
    发明申请
    System and Method for Configurable Multi-standard Receiver 审中-公开
    可配置多标准接收机的系统和方法

    公开(公告)号：US20120026407A1

    公开(公告)日：2012-02-02

    申请号：US13116532

    申请日：2011-05-26

    申请人： Yifeng Zhang ,  Rong Liu ,  Peiqi Xuan ,  Xiaodong Jin

    发明人： Yifeng Zhang ,  Rong Liu ,  Peiqi Xuan ,  Xiaodong Jin

    IPC分类号： H04N5/50 ,  H04B1/16 ,  H04B1/06

    CPC分类号： H04B1/30 ,  H04B1/0032 ,  H04B1/406 ,  H04N5/46 ,  H04N21/42638

    摘要： A configurable multi-standard receiver. A receiver comprises a mixer, a processing module and an analog to digital converter is disclosed to receive multi-standard radio signals. The processing module includes a first selection switch and first parameter control, where the first selection switch configures the processing module as a complex filter or a real-valued filter and the first parameter control configures the characteristics of the filter. Furthermore, the analog to digital converted is preferably implemented using sigma delta modulation to achieve a desired noise shaping. The sigma delta modulation comprises a second selection switch and second parameter control. The second selection switch configures the sigma delta modulation to function as a unit having a complex loop filter or a unit having real-valued loop filters. The second parameter control configures the characteristics of the loop filter. The settings for the first and second selection switches and the first and second control parameters may be stored in a control register.

    摘要翻译： 可配置的多标准接收器。 接收机包括混频器，处理模块和模数转换器，用于接收多标准无线电信号。 处理模块包括第一选择开关和第一参数控制，其中第一选择开关将处理模块配置为复数滤波器或实值滤波器，并且第一参数控制器配置滤波器的特性。 此外，优选地，使用Σ-Δ调制来实现模数转换，以实现期望的噪声整形。 Σ-Δ调制包括第二选择开关和第二参数控制。 第二选择开关将Σ-Δ调制配置为具有复环路滤波器或具有实值环路滤波器的单元的单元。 第二个参数控制配置环路滤波器的特性。 第一和第二选择开关以及第一和第二控制参数的设置可以存储在控制寄存器中。

    Single-clock-based multiple-clock frequency generator
    2.
    发明授权
    Single-clock-based multiple-clock frequency generator 有权
    单时钟多时钟频率发生器

    公开(公告)号：US08595538B2

    公开(公告)日：2013-11-26

    申请号：US12041543

    申请日：2008-03-03

    申请人： Yifeng Zhang ,  Peiqi Xuan ,  Kanyu Cao ,  Xiaodong Jin

    发明人： Yifeng Zhang ,  Peiqi Xuan ,  Kanyu Cao ,  Xiaodong Jin

    IPC分类号： G06F1/00 ,  G06F1/04 ,  H03L7/06

    CPC分类号： H03L7/099 ,  H03L2207/12

    摘要： In an embodiment of the present invention, a clock generator circuit is disclosed to include a phase locked loop (PLL) that is responsive to a reference frequency and operative to generate a single clock frequency and a clock signal quadrature output frequency and a clock signal in-phase output with the frequency of the clock signal quadrature output frequency and the clock signal in-phase output frequency being a fraction of the frequency of the single clock frequency. The PLL includes a single voltage controlled oscillator (VCO) that generates the single clock frequency. A plurality of dividers is included in the clock generator circuit and is responsive to the clock signal quadrature output frequency and the clock signal in-phase output frequency and generates multiple clock frequencies, each clock frequency being a unique frequency, each of the plurality of dividers generating an output, the final output of the plurality of dividers being synchronized to the reference frequency.

    摘要翻译： 在本发明的实施例中，公开了一种时钟发生器电路，其包括响应于参考频率并且可操作以产生单个时钟频率和时钟信号正交输出频率的锁相环（PLL）和时钟信号 相位输出与时钟信号的频率正交输出频率和时钟信号同相输出频率是单个时钟频率频率的一部分。 PLL包括产生单个时钟频率的单个压控振荡器（VCO）。 多个分频器被包括在时钟发生器电路中，并且响应于时钟信号正交输出频率和时钟信号同相输出频率，并且产生多个时钟频率，每个时钟频率是唯一的频率，每个分频器 产生输出，多个分频器的最终输出与参考频率同步。

    Method and apparatus for an LNA with high linearity and improved gain control
    3.
    发明授权
    Method and apparatus for an LNA with high linearity and improved gain control 有权
    具有高线性度和改进的增益控制的LNA的方法和装置

    公开(公告)号：US07463095B1

    公开(公告)日：2008-12-09

    申请号：US11890738

    申请日：2007-08-07

    申请人： Xiaodong Jin ,  Lawrence Tse ,  King Chun Tsai ,  George Chien

    发明人： Xiaodong Jin ,  Lawrence Tse ,  King Chun Tsai ,  George Chien

    IPC分类号： H03F3/04

    CPC分类号： H03G1/0029 ,  H03G1/007 ,  H03G2201/103

    摘要： An analog signal processing circuit comprises a bias circuit, a first circuit including a control input that communicates with the bias circuit, a first terminal that generates an output current, and a second terminal, and a device that communicates with the second terminal of the first circuit, that includes a variable resistor, and that has a resistance that is modulated in response to an input signal to the analog signal processing circuit.

    摘要翻译： 模拟信号处理电路包括偏置电路，包括与偏置电路通信的控制输入的第一电路，产生输出电流的第一端子和第二端子，以及与第一端子的第二端子通信的装置 电路，其包括可变电阻器，并且具有响应于模拟信号处理电路的输入信号而被调制的电阻。

    Signal mixer having a single-ended input and a differential output
    5.
    发明授权
    Signal mixer having a single-ended input and a differential output 有权
    信号混频器具有单端输入和差分输出

    公开(公告)号：US07877075B1

    公开(公告)日：2011-01-25

    申请号：US11487040

    申请日：2006-07-14

    申请人： Xiaodong Jin ,  Lawrence Tse

    发明人： Xiaodong Jin ,  Lawrence Tse

    IPC分类号： H04B1/26

    CPC分类号： H03D7/1425 ,  H03D7/1433 ,  H03D7/145 ,  H03D7/1458 ,  H03D7/1491 ,  H03D2200/0023 ,  H03D2200/0088

    摘要： A single-ended-to-differential mixer includes a differential input circuit having a single-ended input. The differential input circuit is responsive to a single-ended input signal to generate first and second signals. The single-ended-to-differential mixer includes a passive tank circuit in communication between a reference voltage and the differential input circuit. The single-ended-to-differential mixer includes a mixer circuit in communication with the differential input circuit and responsive to the first and second signals and a second input signal to generate a differential mixer output signal.

    摘要翻译： 单端到差分混频器包括具有单端输入的差分输入电路。 差分输入电路响应于单端输入信号以产生第一和第二信号。 单端到差分混频器包括在参考电压和差分输入电路之间通信的无源电路。 单端到差分混频器包括与差分输入电路通信并响应于第一和第二信号的混频器电路和第二输入信号以产生差分混频器输出信号。

    Signal mixer having a single-ended input and a differential output
    7.
    发明授权
    Signal mixer having a single-ended input and a differential output 失效
    信号混频器具有单端输入和差分输出

    公开(公告)号：US07676212B1

    公开(公告)日：2010-03-09

    申请号：US11507304

    申请日：2006-08-21

    申请人： Xiaodong Jin ,  Lawrence Tse

    发明人： Xiaodong Jin ,  Lawrence Tse

    IPC分类号： H04B1/28

    CPC分类号： H03D7/1425 ,  H03D7/1433 ,  H03D7/145 ,  H03D7/1458 ,  H03D7/1491 ,  H03D2200/0023 ,  H03D2200/0088

    摘要： A mixer comprises a differential input circuit that is configured to receive an input signal. The mixer comprises a tank circuit including a tuning capacitor arranged in parallel with an inductor. A resonant frequency of the inductor and tuning capacitor is substantially centered around a predetermined frequency of the input signal. The mixer comprises a mixer circuit that communicates with the differential input circuit and that is configured to receive first and second current signals and a second input signal. The mixer circuit is configured as a Gilbert cell double-balanced switching mixer for generating a differential mixer output signal as a product of the first and second current signals and the second input signal.

    摘要翻译： 混频器包括被配置为接收输入信号的差分输入电路。 混频器包括一个包括与电感器并联布置的调谐电容器的振荡电路。 电感器和调谐电容器的谐振频率基本上以输入信号的预定频率为中心。 混频器包括与差分输入电路通信并被配置为接收第一和第二电流信号和第二输入信号的混频器电路。 混频器电路被配置为吉尔伯特单元双平衡开关混频器，用于产生作为第一和第二电流信号与第二输入信号的乘积的差分混频器输出信号。

    Active bias circuit for low-noise amplifiers
    8.
    发明授权
    Active bias circuit for low-noise amplifiers 有权
    低噪声放大器的主动偏置电路

    公开(公告)号：US07515000B1

    公开(公告)日：2009-04-07

    申请号：US11895973

    申请日：2007-08-28

    申请人： Xiaodong Jin ,  Shuran Wei

    发明人： Xiaodong Jin ,  Shuran Wei

    IPC分类号： H03G3/10

    CPC分类号： H03F1/26 ,  H03F1/30 ,  H03F3/343 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2200/504

    摘要： A low-noise amplifier comprises a first amplification circuit that includes a control terminal and a first terminal. An impedance load communicates with the first terminal. A feedback circuit outputs an output current to the first terminal and that generates a bias current, which is output to the control terminal and is based on a difference between the output current and N times a reference current, where N is greater than zero.

    摘要翻译： 低噪声放大器包括包括控制端和第一端的第一放大电路。 阻抗负载与第一端子通信。 反馈电路将输出电流输出到第一端子并产生偏置电流，该偏置电流输出到控制端子，并且基于输出电流与N大于零的参考电流之间的差值。

    Method and apparatus for an LNA with high linearity and improved gain control
    9.
    发明授权
    Method and apparatus for an LNA with high linearity and improved gain control 有权
    具有高线性度和改进的增益控制的LNA的方法和装置

    公开(公告)号：US07230491B1

    公开(公告)日：2007-06-12

    申请号：US11175943

    申请日：2005-07-05

    申请人： Xiaodong Jin ,  Lawrence Tse ,  King Chun Tsai ,  George Chien

    发明人： Xiaodong Jin ,  Lawrence Tse ,  King Chun Tsai ,  George Chien

    IPC分类号： H03G3/10

    CPC分类号： H03G1/0029 ,  H03G1/007 ,  H03G2201/103

    摘要： A bias circuit for biasing a linear input stage of an amplifier comprises a first MOS device having a size. A second MOS device has a size and is arranged with the first MOS device in a cascode configuration. The second MOS device is operated in a saturation region. A third MOS device has a size and biases the first MOS device in a triode region. A bias switch ratio of the size of the first MOS device to the size of the third MOS device is greater than one.

    摘要翻译： 用于偏置放大器的线性输入级的偏置电路包括具有大小的第一MOS器件。 第二MOS器件具有尺寸并与第一MOS器件配置成共源共栅配置。 第二MOS器件在饱和区域中工作。 第三MOS器件具有尺寸并偏置三极管区域中的第一MOS器件。 第一MOS器件的尺寸与第三MOS器件的尺寸的偏置开关比大于1。