Methods of fabricating semiconductor device

    公开(公告)号:US10431459B2

    公开(公告)日:2019-10-01

    申请号:US15668689

    申请日:2017-08-03

    摘要: An etching target layer is formed on a substrate. An upper mask layer is formed on the etching target layer. A plurality of preliminary mask patterns is formed on the upper mask layer. The plurality of preliminary mask patterns is arranged at a first pitch. Two neighboring preliminary mask patterns of the plurality of preliminary mask patterns define a preliminary opening. An ion beam etching process is performed on the upper mask layer using the plurality of preliminary mask patterns as an etch mask to form a first preliminary-interim-mask pattern and a pair of second preliminary-interim-mask patterns. The first preliminary-interim-mask pattern is formed between one of the pair of second preliminary-interim-mask patterns and the other of the pair of second preliminary-interim-mask patterns.

    Semiconductor memory device
    4.
    发明授权

    公开(公告)号:US10205090B2

    公开(公告)日:2019-02-12

    申请号:US15429494

    申请日:2017-02-10

    IPC分类号: H01L43/08 H01L43/02 H01L27/22

    摘要: A semiconductor memory device that includes at least a lower contact plug on a semiconductor substrate, a magnetic tunnel junction of the lower contact plug, and a barrier pattern on a sidewall of the lower contact plug may further include an insulation pattern on the sidewall of the lower contact plug. The insulation pattern may be between the barrier pattern and the magnetic tunnel junction pattern. The insulation pattern may include an upper portion and a lower portion whose width is greater than a width of the upper portion.