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    Controlling system for gate formation of semiconductor devices
    3.
    发明授权
    Controlling system for gate formation of semiconductor devices 有权
    半导体器件栅极形成控制系统

    公开(公告)号：US07588946B2

    公开(公告)日：2009-09-15

    申请号：US11188324

    申请日：2005-07-25

    申请人： Chia-Tsung Tso ,  Jiun-Hong Lai ,  Mei-Jen Wu ,  Li Te Hsu ,  Pin Chia Su ,  Po-Zen Chen

    发明人： Chia-Tsung Tso ,  Jiun-Hong Lai ,  Mei-Jen Wu ,  Li Te Hsu ,  Pin Chia Su ,  Po-Zen Chen

    IPC分类号： H01L21/00

    CPC分类号： H01L22/12 ,  H01L21/28123 ,  H01L21/76224 ,  H01L22/26 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of controlling gate formation of semiconductor devices includes determining the correlation between the step heights of isolation structures and the over-etching time by measuring step heights of isolation structures, determining an over-etching time based on the step heights, and etching gates using the over-etching time. The method may include an after-etching-inspection to measure the gate profile and fine-tune the gate formation control. Within-wafer uniformity can also be improved by measuring the step height uniformity on a wafer and adjusting gate formation processes.

    摘要翻译： 控制半导体器件的栅极形成的方法包括通过测量隔离结构的阶跃高度来确定隔离结构的台阶高度与过蚀刻时间之间的相关性，基于台阶高度确定过蚀刻时间，以及使用 过蚀刻时间。 该方法可以包括蚀刻检查以测量栅极分布并微调栅极形成控制。 通过测量晶片上的台阶高度均匀性并调整栅极形成工艺，也可以提高晶片内均匀性。

    Controlling system for gate formation of semiconductor devices
    4.
    发明申请
    Controlling system for gate formation of semiconductor devices 有权
    半导体器件栅极形成控制系统

    公开(公告)号：US20070020777A1

    公开(公告)日：2007-01-25

    申请号：US11188324

    申请日：2005-07-25

    申请人： Chia-Tsung Tso ,  Jiun-Hong Lai ,  Mei-Jen Wu ,  Li Hsu ,  Pin Su ,  Po-Zen Chen

    发明人： Chia-Tsung Tso ,  Jiun-Hong Lai ,  Mei-Jen Wu ,  Li Hsu ,  Pin Su ,  Po-Zen Chen

    IPC分类号： H01L21/66 ,  H01L21/76 ,  H01L21/302

    CPC分类号： H01L22/12 ,  H01L21/28123 ,  H01L21/76224 ,  H01L22/26 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of controlling gate formation of semiconductor devices includes determining the correlation between the step heights of isolation structures and the over-etching time by measuring step heights of isolation structures, determining an over-etching time based on the step heights, and etching gates using the over-etching time. The method may include an after-etching-inspection to measure the gate profile and fine-tune the gate formation control. Within-wafer uniformity can also be improved by measuring the step height uniformity on a wafer and adjusting gate formation processes.

    摘要翻译： 控制半导体器件的栅极形成的方法包括通过测量隔离结构的阶跃高度来确定隔离结构的台阶高度与过蚀刻时间之间的相关性，基于台阶高度确定过蚀刻时间，以及使用 过蚀刻时间。 该方法可以包括蚀刻检查以测量栅极分布并微调栅极形成控制。 通过测量晶片上的台阶高度均匀性并调整栅极形成工艺，也可以提高晶片内均匀性。

    Dual damascene process
    6.
    发明授权
    Dual damascene process 有权
    双镶嵌工艺

    公开(公告)号：US07563719B2

    公开(公告)日：2009-07-21

    申请号：US11724284

    申请日：2007-03-15

    申请人： Po-Zen Chen ,  Tzu-Chan Weng ,  Chien-Chung Chen

    发明人： Po-Zen Chen ,  Tzu-Chan Weng ,  Chien-Chung Chen

    IPC分类号： H01L21/311

    CPC分类号： H01L21/31144 ,  H01L21/02063 ,  H01L21/31138 ,  H01L21/76811

    摘要： A dual damascene process. A first photoresist layer with a first opening corresponding to a trench pattern is formed on a dielectric layer. A second photoresist layer with a second opening corresponding to a via pattern smaller then the trench pattern is formed on the first photoresist layer and extends to a portion of the dielectric layer. The second photoresist layer has a material character different from the first photoresist layer. A via etching process using the second photoresist as a mask is performed to form a via hole passing through the dielectric layer. A photoresist ashing process is performed to remove the second photoresist layer. A trench etching process using the first photoresist layer as a mask is performed to form a trench in the upper portion of the dielectric layer. The via etching process, the photoresist ashing process and the trench etching process are performed as a continuous process in one chamber.

    摘要翻译： 双镶嵌工艺。 在电介质层上形成具有对应于沟槽图案的第一开口的第一光致抗蚀剂层。 在第一光致抗蚀剂层上形成具有对应于小于沟槽图案的通孔图案的第二开口的第二光致抗蚀剂层并且延伸到介电层的一部分。 第二光致抗蚀剂层具有与第一光致抗蚀剂层不同的材料特性。 执行使用第二光致抗蚀剂作为掩模的通孔蚀刻工艺，以形成穿过介电层的通孔。 进行光致抗蚀剂灰化处理以去除第二光致抗蚀剂层。 执行使用第一光致抗蚀剂层作为掩模的沟槽蚀刻工艺，以在电介质层的上部形成沟槽。 通孔蚀刻工艺，光致抗蚀剂灰化处理和沟槽蚀刻工艺在一个室中作为连续工艺进行。

    Dual Profile Shallow Trench Isolation Apparatus and System
    8.
    发明申请
    Dual Profile Shallow Trench Isolation Apparatus and System 有权
    双轮廓浅沟槽隔离装置和系统

    公开(公告)号：US20130277790A1

    公开(公告)日：2013-10-24

    申请号：US13454924

    申请日：2012-04-24

    申请人： Chia-Yang Hung ,  Po-Zen Chen ,  Szu-Hung Yang ,  Chih-Cherng Jeng ,  Chih-Kang Chao ,  I-I Cheng

    发明人： Chia-Yang Hung ,  Po-Zen Chen ,  Szu-Hung Yang ,  Chih-Cherng Jeng ,  Chih-Kang Chao ,  I-I Cheng

    IPC分类号： H01L29/06 ,  H01L21/762

    CPC分类号： H01L21/76229 ,  H01L27/1463 ,  H01L27/14643

    摘要： The presented principles describe an apparatus and method of making the same, the apparatus being a semiconductor circuit device, having shallow trench isolation features bounding an active area and a periphery area on a semiconductor substrate to electrically isolate structures in the active area from structures in the periphery area. The shallow trench isolation feature bounding the active area is shallower than the shallow trench isolation feature bounding the periphery area, with the periphery area shallow trench isolation structure being formed through two or more etching steps.

    摘要翻译： 所呈现的原理描述了一种制造它的装置和方法，该装置是半导体电路装置，具有浅沟槽隔离特征，其界定半导体衬底上的有源区域和外围区域，以将活性区域中的结构与 周边地区。 围绕有源区域的浅沟槽隔离特征比围绕边缘区域的浅沟槽隔离特征浅，通过两个或更多个蚀刻步骤形成外围区域浅沟槽隔离结构。

    Dual damascene process
    9.
    发明申请
    Dual damascene process 有权
    双镶嵌工艺

    公开(公告)号：US20080227288A1

    公开(公告)日：2008-09-18

    申请号：US11724284

    申请日：2007-03-15

    申请人： Po-Zen Chen ,  Tzu-Chan Weng ,  Chien-Chung Chen

    发明人： Po-Zen Chen ,  Tzu-Chan Weng ,  Chien-Chung Chen

    IPC分类号： H01L21/4763 ,  H01L21/311

    CPC分类号： H01L21/31144 ,  H01L21/02063 ,  H01L21/31138 ,  H01L21/76811

    摘要： A dual damascene process. A first photoresist layer with a first opening corresponding to a trench pattern is formed on a dielectric layer. A second photoresist layer with a second opening corresponding to a via pattern smaller then the trench pattern is formed on the first photoresist layer and extends to a portion of the dielectric layer. The second photoresist layer has a material character different from the first photoresist layer. A via etching process using the second photoresist as a mask is performed to form a via hole passing through the dielectric layer. A photoresist ashing process is performed to remove the second photoresist layer. A trench etching process using the first photoresist layer as a mask is performed to form a trench in the upper portion of the dielectric layer. The via etching process, the photoresist ashing process and the trench etching process are performed as a continuous process in one chamber.

    摘要翻译： 双镶嵌工艺。 在电介质层上形成具有对应于沟槽图案的第一开口的第一光致抗蚀剂层。 在第一光致抗蚀剂层上形成具有对应于小于沟槽图案的通孔图案的第二开口的第二光致抗蚀剂层并且延伸到介电层的一部分。 第二光致抗蚀剂层具有与第一光致抗蚀剂层不同的材料特性。 执行使用第二光致抗蚀剂作为掩模的通孔蚀刻工艺，以形成穿过介电层的通孔。 进行光致抗蚀剂灰化处理以去除第二光致抗蚀剂层。 执行使用第一光致抗蚀剂层作为掩模的沟槽蚀刻工艺，以在电介质层的上部形成沟槽。 通孔蚀刻工艺，光致抗蚀剂灰化处理和沟槽蚀刻工艺在一个室中作为连续工艺进行。