摘要:
A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The semiconductor device includes a core oxide on the semiconductor substrate in the core area, a portion of the core oxide being nitrided, a first polysilicon pattern on the core oxide, an I/O oxide including pure oxide on the semiconductor substrate in the peripheral area, and a second polysilicon pattern on the I/O oxide.
摘要:
An interconnect structure for a semiconductor device is provided. The interconnect structure for a semiconductor device comprises a substrate having a conductive region thereon, a first dielectric layer having a modified surface portion serving as an etch stop layer and a second dielectric layer having a hardness less than that of the modified surface portion. The interconnect structure for a semiconductor device further comprises a trench-shaped conductive line disposed within the second dielectric layer and a conductive plug disposed within the first dielectric layer and interposed between the trench-shaped conductive line and the conductive region.
摘要:
A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The semiconductor device includes a core oxide on the semiconductor substrate in the core area, a portion of the core oxide being nitrided, a first polysilicon pattern on the core oxide, an I/O oxide including pure oxide on the semiconductor substrate in the peripheral area, and a second polysilicon pattern on the I/O oxide.
摘要:
A method for planarizing a semiconductor structure is disclosed. A semiconductor substrate having a first area in which one or more trenches are formed in a first pattern density, and a second area in which one or more trenches are formed in a second pattern density lower than the first pattern density, is provided. A first dielectric layer is formed above the semiconductor for covering the trenches in the first and second areas. A first chemical mechanical polishing is performed on the first dielectric layer using a predetermined type of slurry for reducing a thickness thereof. The first dielectric layer is then rinsed. A second chemical mechanical polishing is performed on the first dielectric layer using the predetermined type of slurry for further removing the first dielectric layer outside the trenches, thereby reducing a step height variation between surfaces of the first and second areas.
摘要:
A semiconductor structure comprises: a first inter-layer dielectric (ILD) over a substrate; a first metal layer; a plurality of second ILDs over the first ILD; and a plurality of second metal layers, each of the second metal layers is over one of the second ILDs. The first ILD is not cured. It has a k value of between about 2.5 and about 3.0, a pore size of smaller than about 10 Å, and a hardness of greater than about 1.5 Gpa. The second ILDs are cured therefore having lower k values of smaller than about 2.5, pore sizes of greater than about 10 Å, and hardness of smaller than about 1.5 Gpa. The semiconductor structure has reduced plasma charge damage from plasma curing.
摘要:
A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The semiconductor device includes a core oxide on the semiconductor substrate in the core area, a portion of the core oxide being nitrided, a first polysilicon pattern on the core oxide, an I/O oxide including pure oxide on the semiconductor substrate in the peripheral area, and a second polysilicon pattern on the I/O oxide.
摘要:
A method for planarizing a semiconductor structure is disclosed. A semiconductor substrate having a first area in which one or more trenches are formed in a first pattern density, and a second area in which one or more trenches are formed in a second pattern density lower than the first pattern density, is provided. A first dielectric layer is formed above the semiconductor for covering the trenches in the first and second areas. A first chemical mechanical polishing is performed on the first dielectric layer using a predetermined type of slurry for reducing a thickness thereof. The first dielectric layer is then rinsed. A second chemical mechanical polishing is performed on the first dielectric layer using the predetermined type of slurry for further removing the first dielectric layer outside the trenches, thereby reducing a step height variation between surfaces of the first and second areas.
摘要:
A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The semiconductor device includes a core oxide on the semiconductor substrate in the core area, a portion of the core oxide being nitrided, a first polysilicon pattern on the core oxide, an I/O oxide including pure oxide on the semiconductor substrate in the peripheral area, and a second polysilicon pattern on the I/O oxide.
摘要:
A method of manufacturing a semiconductor device having a porous, low-k dielectric layer is provided. A preferred embodiment comprises the steps of forming a porogen-containing, low-k dielectric layer, in the damascene process. In preferred embodiments, pore generation, by e-beam porogen degradation, occurs after the steps of CMP planarizing the damascene copper conductor and depositing a semipermeable cap layer. In alternative embodiments, the cap layer consists essentially of silicon carbide, silicon nitride, Co, W, Al, Ta, Ti, Ni, Ru, and combinations thereof. The semipermeable cap layer is preferably deposited under PECVD conditions such that the cap layer is sufficiently permeable to enable removal of porogen degradation by-products. Preferred embodiments further include an in-situ N2/NH3 treatment before depositing the semipermeable cap layer.
摘要:
A method of manufacturing a semiconductor device having a porous, low-k dielectric layer is provided. A preferred embodiment comprises the steps of forming a porogen-containing, low-k dielectric layer, in the damascene process. In preferred embodiments, pore generation, by e-beam porogen degradation, occurs after the steps of CMP planarizing the damascene copper conductor and depositing a semipermeable cap layer. In alternative embodiments, the cap layer consists essentially of silicon carbide, silicon nitride, Co, W, Al, Ta, Ti, Ni, Ru, and combinations thereof. The semipermeable cap layer is preferably deposited under PECVD conditions such that the cap layer is sufficiently permeable to enable removal of porogen degradation by-products. Preferred embodiments further include an in-situ N2/NH3 treatment before depositing the semipermeable cap layer.