公开(公告)号：US06767780B2

公开(公告)日：2004-07-27

申请号：US10331590

申请日：2002-12-31

申请人： Yong-Sun Sohn ,  Chang-Woo Ryoo ,  Jeong-Youb Lee

发明人： Yong-Sun Sohn ,  Chang-Woo Ryoo ,  Jeong-Youb Lee

IPC分类号： H01L218238

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823892 ,  H01L27/0921 ,  H01L29/1083 ,  H01L29/7833

摘要： A method for fabricating a CMOS transistor is disclosed. The present invention provides a method for producing a CMOS transistor having enhanced performance since a short channel characteristic and operation power can be controlled by the duplicate punch stop layer of the pMOS region and the operation power of the nMOS is also controlled by dopant concentration of the duplicated LDD region combined by the first LDD region and the second LDD region.

摘要翻译： 公开了一种制造CMOS晶体管的方法。 本发明提供了一种具有增强性能的CMOS晶体管的制造方法，因为可以通过pMOS区域的复制冲击阻挡层控制短沟道特性和操作功率，并且nMOS的操作功率也由掺杂剂浓度 由第一LDD区域和第二LDD区域组合的复制LDD区域。

公开(公告)号：US06879006B2

公开(公告)日：2005-04-12

申请号：US10809350

申请日：2004-03-26

申请人： Yong-Sun Sohn ,  Chang-Woo Ryoo ,  Jeong-Youb Lee

发明人： Yong-Sun Sohn ,  Chang-Woo Ryoo ,  Jeong-Youb Lee

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823892 ,  H01L27/0921 ,  H01L29/1083 ,  H01L29/7833

摘要： A method for fabricating a CMOS transistor is disclosed. The present invention provides a method for producing a CMOS transistor having enhanced performance since a short channel characteristic and operation power can be controlled by the duplicate punch stop layer of the pMOS region and the operation power of the nMOS is also controlled by dopant concentration of the duplicated LDD region combined by the first LDD region and the second LDD region.

摘要翻译： 公开了一种制造CMOS晶体管的方法。 本发明提供了一种具有增强性能的CMOS晶体管的制造方法，因为可以通过pMOS区域的复制冲击阻挡层控制短沟道特性和操作功率，并且nMOS的操作功率也由掺杂剂浓度 由第一LDD区域和第二LDD区域组合的复制LDD区域。

公开(公告)号：US20050250299A1

公开(公告)日：2005-11-10

申请号：US11026294

申请日：2004-12-30

申请人： Yong-Sun Sohn ,  Seung-Woo Jin ,  Min-Yong Lee ,  Kyoung-Bong Rouh

发明人： Yong-Sun Sohn ,  Seung-Woo Jin ,  Min-Yong Lee ,  Kyoung-Bong Rouh

IPC分类号： C23C14/48 ,  H01J37/317 ,  H01L21/265 ,  H01L21/336 ,  H01L21/425 ,  H01L29/78

CPC分类号： H01L21/265 ,  H01L21/26513 ,  H01L21/2658

摘要： The present invention provides a method for implanting ions in a semiconductor device capable of compensating for a difference in threshold voltages between a central portion and edge portions of a substrate generated while performing uniform ion implantation to entire surfaces of a substrate and another method for fabricating a semiconductor device capable of improving distribution of transistor parameters inside a substrate by forming a nonuniform channel doping layer or by forming a nonuniform junction profile.

摘要翻译： 本发明提供了一种用于在半导体器件中注入离子的方法，该半导体器件能够补偿在对衬底的整个表面进行均匀的离子注入时产生的衬底的中心部分和边缘部分之间的阈值电压的差异， 半导体器件能够通过形成不均匀的沟道掺杂层或通过形成不均匀的结形状来改善衬底内的晶体管参数的分布。

公开(公告)号：US20110039403A1

公开(公告)日：2011-02-17

申请号：US12913267

申请日：2010-10-27

申请人： Yong-Sun Sohn ,  Seung-Woo Jin ,  Min-Yong Lee ,  Kyoung-Bong Rouh

发明人： Yong-Sun Sohn ,  Seung-Woo Jin ,  Min-Yong Lee ,  Kyoung-Bong Rouh

IPC分类号： H01L21/265

CPC分类号： H01L21/265 ,  H01L21/26513 ,  H01L21/2658

摘要： The present invention provides various methods for implanting ions in a semiconductor device that substantially compensate for a difference in threshold voltages between a central portion and edge portions of a substrate generated while performing uniform ion implantation to entire surfaces of a substrate. Other methods for fabricating a semiconductor device improve distribution of transistor parameters across a substrate by forming a nonuniform channel doping layer or by forming a nonuniform junction profile, across the substrate.

摘要翻译： 本发明提供了用于在半导体器件中注入离子的各种方法，其基本上补偿了在对衬底的整个表面进行均匀离子注入时产生的衬底的中心部分和边缘部分之间的阈值电压的差异。 用于制造半导体器件的其它方法通过形成不均匀的沟道掺杂层或通过在衬底上形成不均匀的结分布来改善晶体管参数跨衬底的分布。

公开(公告)号：US06881987B2

公开(公告)日：2005-04-19

申请号：US10616625

申请日：2003-07-10

申请人： Yong-Sun Sohn

发明人： Yong-Sun Sohn

IPC分类号： H01L21/265 ,  H01L21/324 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78 ,  H01L31/0328 ,  H01L21/336 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L29/1033 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/7833

摘要： The present invention provides a p-channel metal-oxide-semiconductor (pMOS) device having an ultra shallow epi-channel satisfying a high doping concentration required for a device of which gate length is about 30 nm even without using a HALO doping layer and a method for fabricating the same. The pMOS device includes: a semiconductor substrate; a channel doping layer being formed in a surface of the semiconductor substrate and being dually doped with dopants having different diffusion rates; a silicon epi-layer being formed on the channel doping layer, whereby constructing an epi-channel along with the channel doping layer; a gate insulating layer formed on the silicon epi-layer; a gate electrode formed on the gate insulating layer; a source/drain extension region highly concentrated and formed in the semiconductor substrate of lateral sides of the epi-channel; and a source/drain region electrically connected to the source/drain extension region and deeper than the source/drain region.

摘要翻译： 本发明提供一种p沟道金属氧化物半导体（pMOS）器件，其具有满足栅极长度约为30nm的器件所需的高掺杂浓度的超浅外延波长，即使不使用HALO掺杂层和 其制造方法 pMOS器件包括：半导体衬底; 沟道掺杂层形成在半导体衬底的表面中并被掺杂有不同扩散速率的掺杂剂; 在沟道掺杂层上形成硅外延层，由此与沟道掺杂层一起构成外延沟道; 形成在硅外延层上的栅极绝缘层; 形成在所述栅极绝缘层上的栅电极; 源极/漏极延伸区域，其高度集中并形成在外延通道的侧面的半导体衬底中; 以及源极/漏极区域，其电连接到源极/漏极延伸区域并且比源极/漏极区域更深。

公开(公告)号：US07026256B2

公开(公告)日：2006-04-11

申请号：US10746069

申请日：2003-12-24

申请人： Yong-Sun Sohn

发明人： Yong-Sun Sohn

IPC分类号： H01L21/469

CPC分类号： H01L21/76825 ,  H01L21/76822 ,  H01L21/76837

摘要： The method for forming a flowable dielectric layer without micro-voids therein in a semiconductor device is employed to utilize a ultra-violet (UV) bake process. The method includes steps of: forming a plurality of patterns on a semiconductor substrate, wherein narrow and deep gaps are formed therebetween; forming a flowable dielectric layer so as to fill the gaps between the patterns; carrying out a baking process for densifying the flowable dielectric layer from a bottom face thereof; forming a plurality of contact holes by selectively etching the flowable dielectric layer; carrying out a pre-cleaning process in order to remove native oxide and impurity substances on the contact holes; and forming a plurality of contact plugs by filling a conductive material into the contact holes.

摘要翻译： 采用在半导体器件中形成其中没有微孔的可流动介电层的方法来利用紫外线（UV）烘烤工艺。 该方法包括以下步骤：在半导体衬底上形成多个图案，其间形成有窄而深的间隙; 形成可流动的电介质层，以填充图案之间的间隙; 进行从其底面致密化可流动介电层的烘烤工艺; 通过选择性地蚀刻可流动介电层形成多个接触孔; 进行预清洁处理以去除接触孔上的天然氧化物和杂质; 以及通过将导电材料填充到所述接触孔中而形成多个接触插塞。

公开(公告)号：US06953734B2

公开(公告)日：2005-10-11

申请号：US10735742

申请日：2003-12-16

申请人： Jae-Eun Lim ,  Yong-Sun Sohn

发明人： Jae-Eun Lim ,  Yong-Sun Sohn

IPC分类号： H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76224

摘要： The method for manufacturing an STI in a semiconductor device with an enhanced gap-fill property and leakage property is disclosed by introducing a nitridation process instead of forming a liner nitride. The method includes steps of: preparing a semiconductor substrate obtained by a predetermined process on which a pad oxide and a pad nitride are formed on predetermined locations thereof; forming an isolation trench with a predetermined depth in the semiconductor substrate; forming a wall oxide on the trench; forming a liner oxide on the wall oxide and an exposed surface of the pad nitride; carrying out a nitridation process for forming a nitrided oxide; forming an insulating layer over the resultant structure, wherein the isolation trench is filled with the insulating layer; and planarizing a top face of the insulating layer.

摘要翻译： 通过引入氮化处理而不是形成衬里氮化物，公开了具有增强的间隙填充性和漏电特性的半导体器件中的STI的制造方法。 该方法包括以下步骤：制备通过在其预定位置上形成衬垫氧化物和衬垫氮化物的预定工艺获得的半导体衬底; 在半导体衬底中形成具有预定深度的隔离沟槽; 在沟槽上形成壁氧化物; 在壁氧化物上形成衬垫氧化物和衬垫氮化物的暴露表面; 进行用于形成氮化氧化物的氮化工序; 在所得结构上形成绝缘层，其中隔离沟槽填充有绝缘层; 并平坦化绝缘层的顶面。

公开(公告)号：US20050020063A1

公开(公告)日：2005-01-27

申请号：US10746069

申请日：2003-12-24

申请人： Yong-Sun Sohn

发明人： Yong-Sun Sohn

IPC分类号： H01L21/31 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76825 ,  H01L21/76822 ,  H01L21/76837

摘要： The method for forming a flowable dielectric layer without micro-voids therein in a semiconductor device is employed to utilize a ultra-violet (UV) bake process. The method includes steps of: forming a plurality of patterns on a semiconductor substrate, wherein narrow and deep gaps are formed therebetween; forming a flowable dielectric layer so as to fill the gaps between the patterns; carrying out a baking process for densifying the flowable dielectric layer from a bottom face thereof; forming a plurality of contact holes by selectively etching the flowable dielectric layer; carrying out a pre-cleaning process in order to remove native oxide and impurity substances on the contact holes; and forming a plurality of contact plugs by filling a conductive material into the contact holes.

摘要翻译： 采用在半导体器件中形成其中没有微孔的可流动介电层的方法来利用紫外线（UV）烘烤工艺。 该方法包括以下步骤：在半导体衬底上形成多个图案，其间形成有窄而深的间隙; 形成可流动的电介质层，以填充图案之间的间隙; 进行从其底面致密化可流动介电层的烘烤工艺; 通过选择性地蚀刻可流动介电层形成多个接触孔; 进行预清洁处理以去除接触孔上的天然氧化物和杂质; 以及通过将导电材料填充到所述接触孔中而形成多个接触插塞。

公开(公告)号：US06753230B2

公开(公告)日：2004-06-22

申请号：US10330087

申请日：2002-12-30

申请人： Yong-Sun Sohn ,  Sung-Jae Joo

发明人： Yong-Sun Sohn ,  Sung-Jae Joo

IPC分类号： H01L22336

CPC分类号： H01L29/66651 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/105 ,  H01L29/365

摘要： The present invention provides a method for fabricating a semiconductor device with ultra-shallow super-steep-retrograde epi-channel that is able to overcome limitedly useable energies and to enhance manufacturing productivity than using ultra low energy ion implantation technique that has disadvantage of difficulties to get the enough ion beam current as well as that of prolonged processing time. The inventive method includes the steps of: a method for fabricating a semiconductor device with ultra shallow super-steep-retrograde (hereinafter referred as to SSR) epi-channel, comprising the steps of: forming a channel doping layer below a surface of a semiconductor substrate by implanting decaborane; forming an epi-layer on the channel doping layer; forming sequentially a gate dielectric layer and a gate electrode on the epi-layer; forming source/drain extension areas shallower than the channel doping layer by being aligned at edges of the gate electrode; forming a spacers on lateral sides of the gate electrode; and forming source/drain areas deeper than the channel doping layer by being aligned at edges of the spacer through ion implantation onto the substrate.

摘要翻译： 本发明提供了一种制造具有超浅超陡逆转外延通道的半导体器件的方法，其能够克服有限可用能量并提高制造生产率，而不是使用具有难以达到的难度的超低能量离子注入技术 获得足够的离子束电流以及长时间的处理时间。 本发明的方法包括以下步骤：制造具有超浅超陡逆行（下文称为SSR）外延通道的半导体器件的方法，包括以下步骤：在半导体的表面下方形成沟道掺杂层 底物植入十硼烷; 在沟道掺杂层上形成外延层; 在外延层上依次形成栅介质层和栅电极; 通过在栅电极的边缘对准，形成比沟道掺杂层浅的源极/漏极延伸区域; 在栅电极的侧面上形成间隔物; 以及通过在衬底上通过离子注入在间隔物的边缘处对准在沟道掺杂层之上形成源极/漏极区域。

公开(公告)号：US06730568B2

公开(公告)日：2004-05-04

申请号：US10330437

申请日：2002-12-30

申请人： Yong-Sun Sohn

发明人： Yong-Sun Sohn

IPC分类号： H01L21336

CPC分类号： H01L21/823807

摘要： This invention relates to a method for fabricating a semiconductor device with the epi-channel structure, which is adapted to overcome an available energy limitation and to improve the productivity by providing the method of SSR epi Channel doping by boron-fluoride compound ion implantation without using ultra low energy ion implantation and a method for fabricating the semiconductive device with epi-channel structure adapted to prevent the crystal defects caused by the epitaxial growth on ion bombarded and fluorinated channel doping layer. The method for forming the epi-channel of a semiconductor device includes the steps of: forming a channel doping layer below a surface of a semiconductive substrate by implanting boron-fluoride compound ions containing boron; performing an annealing process to remove fluorine ions, injected during above ion implantation, within the channel doping layer; performing the surface treatment process to remove the native oxide layer formed on the surface of the channel doping layer and simultaneously to remove remaining fluorine ions within the channel doping layer; and growing epitaxial layer on the channel doping layer using the selective epitaxial growth method.

摘要翻译： 本发明涉及一种用于制造具有外延通道结构的半导体器件的方法，其适于克服可用的能量限制并通过提供通过硼氟化合物离子注入的SSR外延通道掺杂的方法来提高生产率，而不使用 超低能量离子注入和用于制造具有外延通道结构的半导体器件的方法，其适于防止由离子轰击和氟化沟道掺杂层引起的外延生长引起的晶体缺陷。 用于形成半导体器件的外延沟道的方法包括以下步骤：通过注入含硼的氟化硼化合物离子在半导体衬底的表面下方形成沟道掺杂层; 进行退火处理以去除在离子注入期间注入的氟离子在沟道掺杂层内; 进行表面处理工序以除去形成在沟道掺杂层的表面上的自然氧化物层，同时除去沟道掺杂层内剩余的氟离子; 以及使用选择性外延生长方法在沟道掺杂层上生长外延层。