公开(公告)号：US07936591B2

公开(公告)日：2011-05-03

申请号：US12356722

申请日：2009-01-21

申请人： Kiyotaro Itagaki ,  Yoshihiro Ueda

发明人： Kiyotaro Itagaki ,  Yoshihiro Ueda

IPC分类号： G11C11/00

CPC分类号： G11C11/1675 ,  G11C11/1673

摘要： A word line voltage is applied to a plurality of word lines. A read/write voltage is applied to a plurality of bit lines. The read/write voltage is applied to a plurality of source lines. A word line selector selects the word line and applies the word line voltage. A driver applies a predetermined voltage to the bit line and the source line, thereby supplying a current to the memory cell. A read circuit reads a first current having flowed through the memory cell, and determines data stored in the memory cell. When performing the read, the driver supplies a second current to second bit lines among other bit lines, which are adjacent to the first bit line through which the first current has flowed. The second current generates a magnetic field in a direction to suppress a write error in the memory cell from which data is to be read.

摘要翻译： 字线电压被施加到多个字线。 读/写电压被施加到多个位线。 读/写电压被施加到多条源极线。 字线选择器选择字线并施加字线电压。 驱动器将预定电压施加到位线和源极线，从而向存储器单元提供电流。 读取电路读取已经流过存储器单元的第一电流，并且确定存储在存储单元中的数据。 当执行读取时，驱动器向与第一电流流过的第一位线相邻的其它位线中的第二位线提供第二电流。 第二电流在抑制要从其读取数据的存储单元中的写入错误的方向上产生磁场。

公开(公告)号：US20070206406A1

公开(公告)日：2007-09-06

申请号：US11673241

申请日：2007-02-09

申请人： Yoshihiro Ueda ,  Kenji Tsuchida ,  Tsuneo Inaba ,  Kiyotaro Itagaki

发明人： Yoshihiro Ueda ,  Kenji Tsuchida ,  Tsuneo Inaba ,  Kiyotaro Itagaki

IPC分类号： G11C11/00

CPC分类号： G11C11/16 ,  Y10S977/935

摘要： A spin injection write type magnetic memory device includes memory cells which have a magnetoresistance effect element and a select transistor. The magnetoresistance effect element has one end connected to a first node. The select transistor has a first diffusion area connected to another end of the magnetoresistance effect element and a second diffusion area connected to a second node. A select line extends along a first direction and is connected to a gate electrode of the select transistor. A first interconnect extends along a second direction and is connected to the first node. A second interconnect extends along the second direction and is connected to the second node. Two of the memory cells adjacent along the first direction share the first node. Two of the memory cells adjacent along the second direction share the second node.

摘要翻译： 自旋注入写入型磁存储器件包括具有磁阻效应元件和选择晶体管的存储单元。 磁阻效应元件的一端连接到第一节点。 选择晶体管具有连接到磁阻效应元件的另一端的第一扩散区域和连接到第二节点的第二扩散区域。 选择线沿着第一方向延伸并连接到选择晶体管的栅电极。 第一互连沿着第二方向延伸并连接到第一节点。 第二互连沿着第二方向延伸并且连接到第二节点。 沿着第一方向相邻的两个存储单元共享第一节点。 沿着第二方向相邻的两个存储单元共享第二节点。

公开(公告)号：US08036015B2

公开(公告)日：2011-10-11

申请号：US12536341

申请日：2009-08-05

申请人： Yoshihiro Ueda ,  Kenji Tsuchida ,  Kiyotaro Itagaki

发明人： Yoshihiro Ueda ,  Kenji Tsuchida ,  Kiyotaro Itagaki

IPC分类号： G11C11/00 ,  G11C7/10

CPC分类号： G11C13/00 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C13/0004 ,  G11C13/004 ,  G11C29/02 ,  G11C29/026 ,  G11C2013/0054 ,  G11C2213/79

摘要： A resistive memory includes a plurality of memory cells, a plurality of reference cells having mutually different resistance values, at least one sense amplifier having a first input terminal connected to one selected memory cell which is selected from the plurality of memory cells at a time of read, and a second input terminal connected to one selected reference cell which is selected from the plurality of reference cells at the time of read, and one latch circuit which holds offset information of the at least one sense amplifier. The resistive memory further includes a decoder which selects, in accordance with the offset information, the one selected reference cell from the plurality of reference cells, and connects the one selected reference cell to the second input terminal of the at least one sense amplifier.

摘要翻译： 电阻存储器包括多个存储单元，具有相互不同的电阻值的多个参考单元，至少一个读出放大器，其具有连接到从多个存储单元中选择的一个选定存储单元的第一输入端， 读取，以及连接到在读取时从多个参考单元中选择的一个选择的参考单元的第二输入端子，以及保持所述至少一个读出放大器的偏移信息的一个锁存电路。 电阻存储器还包括解码器，其根据偏移信息从多个参考单元中选择一个选定的参考单元，并将所选择的一个参考单元连接到至少一个读出放大器的第二输入端。

公开(公告)号：US20090257274A1

公开(公告)日：2009-10-15

申请号：US12400262

申请日：2009-03-09

申请人： Kiyotaro Itagaki ,  Tsuneo Inaba ,  Yoshihiro Ueda ,  Yoshiaki Asao

发明人： Kiyotaro Itagaki ,  Tsuneo Inaba ,  Yoshihiro Ueda ,  Yoshiaki Asao

IPC分类号： G11C11/16 ,  G11C11/14

CPC分类号： G11C11/5607 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/75 ,  G11C2213/78

摘要： A semiconductor memory device includes n resistance change elements which are arranged in one cell, have a low-resistance state and a high resistance state, are connected in series or parallel, have different resistance values in the same resistance state, and change between the low-resistance state and the high-resistance state under different conditions, and a write circuit which is connected to one end of the n resistance change elements, and applies a pulse current m (1≦m≦n) times to the n resistance change elements during a write operation. Letting Im be a current value of an mth pulse current, condition I1>I2> . . . >Im holds.

摘要翻译： 半导体存储器件包括在一个单元中布置的具有低电阻状态和高电阻状态的n个电阻变化元件串联或并联连接，在相同电阻状态下具有不同的电阻值，并且在低电平 电阻状态和不同条件下的高电阻状态，以及与n个电阻变化元件的一端连接的写入电路，并向n个电阻施加脉冲电流m（1 <= m <= n）次 在写入操作期间更改元素。 令Im为第m个脉冲电流的当前值，条件I1> I2>。 。 。 > Im持有。

公开(公告)号：US07916522B2

公开(公告)日：2011-03-29

申请号：US12400262

申请日：2009-03-09

申请人： Kiyotaro Itagaki ,  Tsuneo Inaba ,  Yoshihiro Ueda ,  Yoshiaki Asao

发明人： Kiyotaro Itagaki ,  Tsuneo Inaba ,  Yoshihiro Ueda ,  Yoshiaki Asao

IPC分类号： G11C11/15

CPC分类号： G11C11/5607 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/75 ,  G11C2213/78

摘要： A semiconductor memory device includes n resistance change elements which are arranged in one cell, have a low-resistance state and a high resistance state, are connected in series or parallel, have different resistance values in the same resistance state, and change between the low-resistance state and the high-resistance state under different conditions, and a write circuit which is connected to one end of the n resistance change elements, and applies a pulse current m (1≦m≦n) times to the n resistance change elements during a write operation. Letting Im be a current value of an mth pulse current, condition I1>I2> . . . >Im holds.

摘要翻译： 半导体存储器件包括在一个单元中布置的具有低电阻状态和高电阻状态的n个电阻变化元件串联或并联连接，在相同电阻状态下具有不同的电阻值，并且在低电平 电阻状态和不同条件下的高电阻状态，以及与n个电阻变化元件的一端连接的写入电路，并向n个电阻变化元件施加脉冲电流m（1＆nlE; m＆nlE; n）次 在写操作期间。 令Im为第m个脉冲电流的当前值，条件I1> I2>。 。 。 > Im持有。

公开(公告)号：US07545672B2

公开(公告)日：2009-06-09

申请号：US11673241

申请日：2007-02-09

申请人： Yoshihiro Ueda ,  Kenji Tsuchida ,  Tsuneo Inaba ,  Kiyotaro Itagaki

发明人： Yoshihiro Ueda ,  Kenji Tsuchida ,  Tsuneo Inaba ,  Kiyotaro Itagaki

IPC分类号： G11C11/00

CPC分类号： G11C11/16 ,  Y10S977/935

摘要： A spin injection write type magnetic memory device includes memory cells which have a magnetoresistance effect element and a select transistor. The magnetoresistance effect element has one end connected to a first node. The select transistor has a first diffusion area connected to another end of the magnetoresistance effect element and a second diffusion area connected to a second node. A select line extends along a first direction and is connected to a gate electrode of the select transistor. A first interconnect extends along a second direction and is connected to the first node. A second interconnect extends along the second direction and is connected to the second node. Two of the memory cells adjacent along the first direction share the first node. Two of the memory cells adjacent along the second direction share the second node.

摘要翻译： 自旋注入写入型磁存储器件包括具有磁阻效应元件和选择晶体管的存储单元。 磁阻效应元件的一端连接到第一节点。 选择晶体管具有连接到磁阻效应元件的另一端的第一扩散区域和连接到第二节点的第二扩散区域。 选择线沿着第一方向延伸并连接到选择晶体管的栅电极。 第一互连沿着第二方向延伸并连接到第一节点。 第二互连沿着第二方向延伸并且连接到第二节点。 沿着第一方向相邻的两个存储单元共享第一节点。 沿着第二方向相邻的两个存储单元共享第二节点。

公开(公告)号：US20070258282A1

公开(公告)日：2007-11-08

申请号：US11682934

申请日：2007-03-07

申请人： Yoshihiro UEDA ,  Tsuneo Inaba ,  Yuui Shimizu ,  Kiyotaro Itagaki

发明人： Yoshihiro UEDA ,  Tsuneo Inaba ,  Yuui Shimizu ,  Kiyotaro Itagaki

IPC分类号： G11C11/00

CPC分类号： G11C11/16

摘要： A magnetic memory device includes a magnetoresistance element which has first and second ends. First data is written into the magnetoresistance element by an electric current flowing from the first end to the second end. Second data is written into the magnetoresistance element by an electric current flowing from the second end to the first end. A first p-type MOSFET has one end connected to the first end. A second p-type MOSFET has one end connected to the second end. A first n-type MOSFET has one end connected to the first end. A second n-type MOSFET has one end connected to the second end. A current source circuit is connected to each another end of the first and second p-type MOSFETs and supplies an electric current. A current sink circuit is connected to each another end of the first and second n-type MOSFETs and draws an electric current.

摘要翻译： 磁存储器件包括具有第一和第二端的磁阻元件。 第一数据通过从第一端流到第二端的电流写入磁阻元件。 通过从第二端流到第一端的电流将第二数据写入磁阻元件。 第一p型MOSFET的一端连接到第一端。 第二p型MOSFET的一端连接到第二端。 第一n型MOSFET的一端连接到第一端。 第二个n型MOSFET的一端连接到第二端。 电流源电路连接到第一和第二p型MOSFET的另一端并提供电流。 电流吸收电路连接到第一和第二n型MOSFET的另一端，并且吸收电流。

公开(公告)号：US08334551B2

公开(公告)日：2012-12-18

申请号：US13120987

申请日：2009-08-25

申请人： Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Hideaki Aochi ,  Akihiro Nitayama

发明人： Kiyotaro Itagaki ,  Yoshihisa Iwata ,  Hiroyasu Tanaka ,  Masaru Kidoh ,  Ryota Katsumata ,  Masaru Kito ,  Hideaki Aochi ,  Akihiro Nitayama

IPC分类号： H01L29/792 ,  G11C11/34

CPC分类号： H01L27/1157 ,  G11C5/02 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/7926

摘要： Each of the memory blocks includes: a first conductive layer expanding in parallel to the substrate over the first area, n layers of the first conductive layers being formed in a lamination direction and shared by the plurality of memory strings; a first semiconductor layer; and an electric charge accumulation layer. The memory strings are arranged with m columns in a second direction for each of the memory blocks. The wiring layers are arranged in the second direction, formed to extend to the vicinity of one end of the first conductive layer in the first direction from one side of the memory block, and connected via contact plugs to the first conductive layers. A relation represented by (Formula 1) is satisfied: (Formula 1) m>=n

摘要翻译： 每个存储块包括：在第一区域上平行于衬底扩展的第一导电层，n个第一导电层的层以层叠方向形成并由多个存储器串共享; 第一半导体层; 和电荷蓄积层。 对于每个存储块，存储器串按第二方向布置有m列。 布线层沿第二方向布置，形成为从存储块的一侧沿第一方向延伸到第一导电层的一端附近，并且经由接触插塞连接到第一导电层。 满足式（1）所示的关系：（式1）m> = n

公开(公告)号：US08107286B2

公开(公告)日：2012-01-31

申请号：US12684349

申请日：2010-01-08

申请人： Kiyotaro Itagaki ,  Yoshiaki Fukuzumi ,  Yoshihisa Iwata

发明人： Kiyotaro Itagaki ,  Yoshiaki Fukuzumi ,  Yoshihisa Iwata

IPC分类号： G11C16/26

CPC分类号： H01L27/11578 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3418 ,  H01L27/11582

摘要： A nonvolatile semiconductor memory device comprises: a memory cell array having a plurality of memory strings each having a plurality of memory cells connected in series; and a control circuit configured to execute a read operation for reading data from the memory cells included in a selected memory string from among the plurality of memory strings. During the read operation, the control circuit is configured to apply a first voltage to a gate of at least one of the memory cells in a non-selected memory string not subject to the read operation, and apply a second voltage lower than the first voltage to a gate of another of the memory cells in the non-selected memory string not subject to the read operation.

摘要翻译： 非易失性半导体存储器件包括：具有多个存储器串的存储单元阵列，每个存储器串均具有串联连接的多个存储器单元; 以及控制电路，被配置为执行用于从所述多个存储器串中的所选择的存储器串中包括的存储单元读取数据的读取操作。 在读取操作期间，控制电路被配置为将第一电压施加到不经过读取操作的未选择的存储器串中的至少一个存储器单元的栅极，并施加低于第一电压的第二电压 到没有进行读取操作的未选择的存储器串中的另一个存储器单元的门。

公开(公告)号：US08873330B2

公开(公告)日：2014-10-28

申请号：US13417503

申请日：2012-03-12

申请人： Fumihiro Kono ,  Kiyotaro Itagaki

发明人： Fumihiro Kono ,  Kiyotaro Itagaki

IPC分类号： G11C8/00 ,  G06F13/16 ,  G11C16/08 ,  G11C16/04

CPC分类号： G11C16/08 ,  G06F13/1694 ,  G11C16/0483

摘要： A plurality of address conversion circuits are provided for memory cores respectively, and convert logical address data supplied from outside to physical address data. In an interleave operation, the address conversion circuits output the logical address data as the physical address data without converting the logical address data when a first memory core is to be accessed earlier than a second memory core, whereas output address data obtained by adding a certain value to the logical address data as the physical address data when the second memory core is to be accessed earlier than the first memory core.

摘要翻译： 分别为存储器核提供多个地址转换电路，并将从外部提供的逻辑地址数据转换为物理地址数据。 在交错操作中，地址转换电路输出逻辑地址数据作为物理地址数据，而不需要在比第二存储器核心更先访问第一存储器核心时转换逻辑地址数据，而输出地址数据 作为物理地址数据的逻辑地址数据的值作为第一存储器核心的第二存储器核心的存取时间。