公开(公告)号：US06815741B2

公开(公告)日：2004-11-09

申请号：US10624612

申请日：2003-07-23

申请人： Yoshihisa Fujisaki ,  Yukio Takano ,  Tsutomu Ishiba

发明人： Yoshihisa Fujisaki ,  Yukio Takano ,  Tsutomu Ishiba

IPC分类号： H01L2980

CPC分类号： H01L29/32 ,  C30B15/00 ,  C30B29/42 ,  H01L29/207 ,  H01L2924/0002 ,  H01L2924/00

摘要： By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and minimum value of the lattice distortions of a III-V single crystal at a normal temperature is set to at most 4×10−5, and the density of Si atoms contained in the III-V single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent material is the III-V single crystal can be made uniform.

公开(公告)号：US06294804B1

公开(公告)日：2001-09-25

申请号：US08943593

申请日：1997-10-03

申请人： Yoshihisa Fujisaki ,  Yukio Takano ,  Tsutomu Ishiba

发明人： Yoshihisa Fujisaki ,  Yukio Takano ,  Tsutomu Ishiba

IPC分类号： H01L2920

CPC分类号： H01L29/32 ,  C30B15/00 ,  C30B29/42 ,  H01L29/207 ,  H01L2924/0002 ,  H01L2924/00

摘要： By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements inthe wafer. The difference between the maximum value and minimum value of the lattice distortions of a GaAs single crystal at a normal temperature is set to at most 4×10−5, and the density of Si atoms contained in the GaAs single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent matrial is the GaAs single crystal can be made uniform.

摘要翻译： 通过利用晶片中的晶格畸变分布与场效应晶体管的阈值电压分布之间的强相关性，晶片中晶格畸变的分布减小，从而减轻半导体的特性分布 砷化镓单晶在正常温度下的晶格畸变的最大值和最小值之间的差设定为至多4×10 -5，GaAs单晶中所含的Si原子的密度设定为 最多为1×10 16 cm -3，由此可以使母体为GaAs单晶的半导体元件的特性均匀。

公开(公告)号：US5733805A

公开(公告)日：1998-03-31

申请号：US457569

申请日：1995-06-01

申请人： Yoshihisa Fujisaki ,  Yukio Takano ,  Tsutomu Ishiba

发明人： Yoshihisa Fujisaki ,  Yukio Takano ,  Tsutomu Ishiba

IPC分类号： C30B15/00 ,  H01L29/207 ,  H01L29/32 ,  H01L21/301

CPC分类号： H01L29/32 ,  C30B15/00 ,  C30B29/42 ,  H01L29/207 ,  H01L2924/0002

摘要： By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements inthe wafer. The difference between the maximum value and minimum value of the lattice distortions of a GaAs single crystal at a normal temperature is set to at most 4.times.10.sup.-5, and the density of Si atoms contained in the GaAs single crystal is set to at most 1.times.10.sup.16 cm.sup.-3, whereby the characteristics of semiconductor elements whose parent matrial is the GaAs single crystal can be made uniform.

摘要翻译： 通过利用晶片中的晶格畸变分布与场效应晶体管的阈值电压分布之间的强相关性，晶片中晶格畸变的分布减小，从而减轻半导体的特性分布 晶片中的元素 GaAs单晶在正常温度下的晶格畸变的最大值和最小值之间的差设定为4×10-5以下，将GaAs单晶中所含的Si原子的密度设定为1×1016 cm以下 -3，由此可以使母体为GaAs单晶的半导体元件的特性均匀。

公开(公告)号：US06630697B2

公开(公告)日：2003-10-07

申请号：US09911481

申请日：2001-07-25

申请人： Yoshihisa Fujisaki ,  Yukio Takano ,  Tsutomu Ishiba

发明人： Yoshihisa Fujisaki ,  Yukio Takano ,  Tsutomu Ishiba

IPC分类号： H01L2980

CPC分类号： H01L29/32 ,  C30B15/00 ,  C30B29/42 ,  H01L29/207 ,  H01L2924/0002 ,  H01L2924/00

摘要： By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer si reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and minimum value of the lattice distortions of a GaAs single crystal at a normal temperature is set to at most 4×10−5, and the density of Si atoms contained in the GaAs single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent material is the GaAs single crystal can be made uniform.

摘要翻译： 通过利用晶片中的晶格失真分布与场效应晶体管的阈值电压分布之间的强烈的相关性，晶片si中晶格畸变的分布减小，从而减轻半导体的特性分布 晶片中的元素。 将GaAs单晶在正常温度下的晶格畸变的最大值与最小值的差设定为4×10 -5以下，将GaAs单晶中所含的Si原子的密度设定为最多 1×10 16 cm -3，由此可以使其母材为GaAs单晶的半导体元件的特性均匀。

公开(公告)号：US06297523B1

公开(公告)日：2001-10-02

申请号：US08108499

申请日：1993-08-18

申请人： Yoshihisa Fujisaki ,  Yukio Takano ,  Tsutomu Ishiba

发明人： Yoshihisa Fujisaki ,  Yukio Takano ,  Tsutomu Ishiba

IPC分类号： H01L2976

CPC分类号： H01L29/32 ,  C30B15/00 ,  C30B29/42 ,  H01L29/207

摘要： By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and minimum value of the lattice distortions of a GaAs single crystal at a normal temperature is set to at most 4×10−5 and the density of Si atoms contained in the GaAs single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent material is the GaAs single crystal can be made uniform.

摘要翻译： 通过利用晶片中的晶格畸变分布与场效应晶体管的阈值电压分布之间的强相关性，晶片中晶格畸变的分布减小，从而减轻半导体的特性分布 晶片中的元素。 将GaAs单晶在正常温度下的晶格畸变的最大值和最小值的差设定为4×10-5以下，将GaAs单晶中所含有的Si原子的密度设定为1×1016cm -1以下， 3，由此能够使母材为GaAs单晶的半导体元件的特性均匀。

公开(公告)号：US5770873A

公开(公告)日：1998-06-23

申请号：US457584

申请日：1995-06-01

申请人： Yoshihisa Fujisaki ,  Yukio Takano ,  Tsutomu Ishiba

发明人： Yoshihisa Fujisaki ,  Yukio Takano ,  Tsutomu Ishiba

IPC分类号： C30B15/00 ,  H01L29/207 ,  H01L29/32 ,  H01L29/20 ,  H01L29/812

CPC分类号： H01L29/32 ,  C30B15/00 ,  C30B29/42 ,  H01L29/207 ,  H01L2924/0002

摘要： By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and the minimum value of the lattice distortions of a GaAs single crystal at a normal temperature is set to at most 4.times.10.sup.-5, and the density of Si atoms contained in the GaAs single crystal is set to at most 1.times.10.sup.16 cm.sup.-3, whereby the characteristics of semiconductor elements whose parent material (substrate) is the GaAs single crystal can be made uniform.

摘要翻译： 通过利用晶片中的晶格畸变分布与场效应晶体管的阈值电压分布之间的强相关性，晶片中晶格畸变的分布减小，从而减轻半导体的特性分布 晶片中的元素。 将GaAs单晶在正常温度下的晶格畸变的最大值与最小值的差设定为4×10 -5以下，将GaAs单晶中含有的Si原子的密度设定为1×1016以下 cm-3，由此可以使母材（衬底）为GaAs单晶的半导体元件的特性均匀。

公开(公告)号：US20100061132A1

公开(公告)日：2010-03-11

申请号：US12516690

申请日：2006-12-07

申请人： Yoshihisa Fujisaki ,  Satoru Hanzawa ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki ,  Norikatsu Takaura

发明人： Yoshihisa Fujisaki ,  Satoru Hanzawa ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki ,  Norikatsu Takaura

IPC分类号： G11C11/00 ,  H01L45/00 ,  G11C5/02 ,  G11C7/00

CPC分类号： H01L45/144 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2213/75 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233

摘要： In a semiconductor storage device such as a phase change memory, a technique which can realize high integration is provided. The semiconductor storage device includes a phase change thin film 101 having two stable phases of a crystal state with low electric resistance and an amorphous state with high electric resistance, upper plug electrodes 102 and 103 provided on one side of the phase change thin film 101, a lower electrode 104 provided on the other side of the phase change thin film 101, a selecting transistor 114 whose drain/source terminals are connected to the upper plug electrode 102 and the lower electrode 104, and a selecting transistor 115 whose drain/source terminals are connected to the upper plug electrode 103 and the lower electrode 104, and a first memory cell is configured with the selecting transistor 114 and a phase change region 111 in the phase change thin film 101 sandwiched between the upper plug electrode 102 and the lower electrode 104, and a second memory cell is configured with the selecting transistor 115 and a phase change region 112 in the phase change thin film 101 sandwiched between the upper plug electrode 103 and the lower electrode 104.

摘要翻译： 在诸如相变存储器的半导体存储装置中，提供了可以实现高集成度的技术。 半导体存储装置包括：具有低电阻的晶体状态的两个稳定相和具有高电阻的非晶态的相变薄膜101，设置在相变薄膜101一侧的上部插塞电极102和103， 设置在相变薄膜101的另一侧的下部电极104，漏极/源极端子连接到上部插塞电极102和下部电极104的选择晶体管114，以及选择晶体管115，其漏极/源极端子 连接到上插头电极103和下电极104，并且第一存储单元配置有夹在上插头电极102和下电极之间的相变薄膜101中的选择晶体管114和相变区域111 104，并且第二存储单元配置有夹在b中的相变薄膜101中的选择晶体管115和相变区域112 在上塞电极103和下电极104之间。

公开(公告)号：US20090052231A1

公开(公告)日：2009-02-26

申请号：US12162702

申请日：2006-02-02

申请人： Kenzo Kurotsuchi ,  Norikatsu Takaura ,  Yoshihisa Fujisaki

发明人： Kenzo Kurotsuchi ,  Norikatsu Takaura ,  Yoshihisa Fujisaki

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2213/79 ,  H01L27/24

摘要： A semiconductor device capable of high-speed read and has a high data-retention characteristic is provided. In a semiconductor device including a memory array having a plurality of memory cells provided at intersecting points of a plurality of word lines and a plurality of bit lines, where each memory cell includes an information memory section and a select element, when information is programmed by a first pulse (reset operation) for programming information flowing in the bit line and a second pulse (set operation) different from the first pulse and information is read by a third pulse (read operation), current directions of the second pulse and the third pulse are opposite to each other.

摘要翻译： 提供了一种能够高速读取并具有高数据保持特性的半导体器件。 在包括具有设置在多个字线和多个位线的交叉点处的多个存储单元的存储器阵列的半导体器件中，其中每个存储单元包括信息存储器部分和选择元件，当信息由 用于编程在位线中流动的信息的第一脉冲（复位操作）和与第一脉冲和信息不同的第二脉冲（置位操作）被第三脉冲（读操作）读取，第二脉冲和第三脉冲 脉冲彼此相反。

公开(公告)号：US06818523B2

公开(公告)日：2004-11-16

申请号：US10602644

申请日：2003-06-25

申请人： Hiroshi Miki ,  Keiko Kushida ,  Yasuhiro Shimamoto ,  Shinichiro Takatani ,  Yoshihisa Fujisaki ,  Hiromi Nakai

发明人： Hiroshi Miki ,  Keiko Kushida ,  Yasuhiro Shimamoto ,  Shinichiro Takatani ,  Yoshihisa Fujisaki ,  Hiromi Nakai

IPC分类号： Y01L2120

CPC分类号： H01L28/75 ,  H01L28/55 ,  H01L28/57 ,  H01L28/60

摘要： A method for forming a semiconductor storage device includes steps of forming a memory cell transistor, forming a first plug connected to the memory cell transistor, forming a second plug of a hydrogen diffusion inhibiting layer, forming capacitor electrodes and a capacitor insulator between the capacitor electrodes and forming a hydrogen adsorption inhibiting layer.

摘要翻译： 一种形成半导体存储装置的方法，包括：形成存储单元晶体管，形成连接到存储单元晶体管的第一插头，形成氢扩散抑制层的第二插头，在电容器电极之间形成电容器电极和电容器绝缘体 并形成氢吸附抑制层。

公开(公告)号：US06396092B1

公开(公告)日：2002-05-28

申请号：US09381396

申请日：1999-09-20

申请人： Shinichiro Takatani ,  Hiroshi Miki ,  Keiko Kushida ,  Yoshihisa Fujisaki ,  Kazuyoshi Torii

发明人： Shinichiro Takatani ,  Hiroshi Miki ,  Keiko Kushida ,  Yoshihisa Fujisaki ,  Kazuyoshi Torii

IPC分类号： H01L2906

CPC分类号： H01L28/55 ,  H01L28/60

摘要： A semiconductor device includes a capacitor having a lower electrode (102), a high-dielectric-constant or ferroelectric thin film (103), and an upper electrode (104) which are subsequently stacked. An impurity having an action of suppressing the catalytic activity of a metal or a conductive oxide constituting the electrode is added to the upper electrode (104). The addition of the impurity is effective to prevent inconveniences such as a reduction in capacitance, an insulation failure, and the peeling of the electrode due to hydrogen heat-treatment performed after formation of the upper electrode (104), and to improve the long-term reliability.

摘要翻译： 半导体器件包括随后堆叠的具有下电极（102），高介电常数或铁电薄膜（103）和上电极（104）的电容器。 具有抑制构成电极的金属或导电氧化物的催化活性的作用的杂质被添加到上电极（104）。 杂质的添加对于防止在形成上电极（104）之后进行的氢热处理等电容的减少，绝缘失效以及电极的剥离等不良情况是有效的， 长期可靠性。