Memory device and manufacturing method the same
    3.
    发明授权
    Memory device and manufacturing method the same 有权
    存储器件和制造方法相同

    公开(公告)号:US08030643B2

    公开(公告)日:2011-10-04

    申请号:US11389238

    申请日:2006-03-27

    IPC分类号: G06K19/06

    摘要: A semiconductor device that can transmit and receive data without contact is popular partly as some railway passes, electronic money cards, and the like; however, it has been a prime task to provide an inexpensive semiconductor device for further popularization. In view of the above current conditions, a semiconductor device of the present invention includes a memory with a simple structure for providing an inexpensive semiconductor device and a manufacturing method thereof. A memory element included in the memory includes a layer containing an organic compound, and a source electrode or a drain electrode of a TFT provided in the memory element portion is used as a conductive layer which forms a bit line of the memory element.

    摘要翻译: 可以在没有接触的情况下发送和接收数据的半导体器件部分地受到一些铁路通行证,电子货币卡等的普及; 然而,提供便宜的半导体器件以进一步普及是主要的任务。 鉴于上述现有条件,本发明的半导体器件包括具有用于提供便宜的半导体器件的简单结构的存储器及其制造方法。 包括在存储器中的存储元件包括含有有机化合物的层,并且将设置在存储元件部分中的TFT的源电极或漏电极用作形成存储元件的位线的导电层。

    Nonvolatile semiconductor memory device
    6.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号:US08212302B2

    公开(公告)日:2012-07-03

    申请号:US11723484

    申请日:2007-03-20

    IPC分类号: H01L29/76

    摘要: A nonvolatile semiconductor memory device which is superior in writing property and charge holding property, including a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions, and a first insulating layer, a floating gate, a second insulating layer, and a control gate over the semiconductor substrate. The floating gate includes at least two layers. It is preferable that a band gap of a first layer included in the floating gate, which is in contact with the first insulating layer, be smaller than that of the semiconductor substrate. For example, it is preferable that the band gap of the semiconductor material for forming the floating gate be smaller than that of the channel formation region in the semiconductor substrate by 0.1 eV or more. This is because, by lowering the bottom energy level of a conduction band of the floating gate electrode than that of the channel formation region in the semiconductor substrate, a carrier injecting property and a charge holding property are improved.

    摘要翻译: 一种非易失性半导体存储器件,其特征在于具有在一对杂质区域之间形成沟道形成区域的半导体衬底和第一绝缘层,浮置栅极,第二绝缘层, 以及半导体衬底上的控制栅极。 浮栅包括至少两层。 与第一绝缘层接触的浮栅中包含的第一层的带隙优选小于半导体衬底的带隙。 例如,优选用于形成浮置栅极的半导体材料的带隙比半导体衬底中的沟道形成区域的带隙小0.1eV以上。 这是因为通过降低浮置栅电极的导带的底部能级比半导体衬底中的沟道形成区的底部能级降低,因此提高了载流子注入性和电荷保持性。

    Nonvolatile semiconductor memory device
    7.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号:US07786526B2

    公开(公告)日:2010-08-31

    申请号:US11730184

    申请日:2007-03-29

    IPC分类号: H01L29/792

    摘要: It is an object of the present invention to provide a nonvolatile semiconductor memory device which has superior writing characteristics and electric charge retention characteristics. In addition, it is an object of the present invention to provide a nonvolatile semiconductor memory device in which a writing voltage can be reduced. The nonvolatile semiconductor memory device includes a semiconductor region with a channel formation region formed between a pair of impurity regions which are formed to be apart from each other; and a first insulating layer, a charge accumulation layer, a second insulating layer, and a control gate are formed in a location which is a top layer portion of the semiconductor region and which roughly overlaps with the channel formation region. The charge accumulation layer is insulative and is formed as a layer in which electric charge can be trapped.

    摘要翻译: 本发明的目的是提供一种具有优异的写入特性和电荷保持特性的非易失性半导体存储器件。 此外,本发明的目的是提供一种可以减小写入电压的非易失性半导体存储器件。 非易失性半导体存储器件包括:半导体区域,其具有在形成为彼此分开的一对杂质区域之间形成的沟道形成区域; 并且在作为半导体区域的顶层部分并且与沟道形成区域大致重叠的位置处形成第一绝缘层,电荷累积层,第二绝缘层和控制栅极。 电荷蓄积层是绝缘的,并且形成为能够俘获电荷的层。

    Memory element and semiconductor device
    8.
    发明授权
    Memory element and semiconductor device 有权
    存储元件和半导体器件

    公开(公告)号:US08604547B2

    公开(公告)日:2013-12-10

    申请号:US11795476

    申请日:2006-02-07

    IPC分类号: H01L27/12 H01L21/70

    摘要: It is an object of the present invention to provide a nonvolatile memory device, in which additional writing is possible other than in manufacturing and forgery and the like due to rewriting can be prevented, and a semiconductor device having the memory device. It is another object of the present invention to provide an inexpensive and nonvolatile memory device with high reliability and a semiconductor device. According to one feature of the present invention, a memory device includes a first conductive layer formed over an insulating surface, a second conductive layer, a first insulating layer interposed between the first conductive layer and the second conductive layer, and a second insulating layer which covers a part of the first conductive layer, wherein the first insulating layer covers an edge portion of the first conductive layer, the insulating surface, and the second insulating layer.

    摘要翻译: 本发明的一个目的是提供一种非易失性存储器件,其中可以除了制造和伪造等以外的其他写入可能被改写,以及具有存储器件的半导体器件。 本发明的另一个目的是提供一种具有高可靠性的廉价且非易失性的存储器件和半导体器件。 根据本发明的一个特征,一种存储器件包括:在绝缘表面上形成的第一导电层,第二导电层,介于第一导电层和第二导电层之间的第一绝缘层;以及第二绝缘层, 覆盖第一导电层的一部分,其中第一绝缘层覆盖第一导电层,绝缘表面和第二绝缘层的边缘部分。

    Nonvolatile semiconductor memory device
    9.
    发明申请
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号:US20070228449A1

    公开(公告)日:2007-10-04

    申请号:US11730184

    申请日:2007-03-29

    IPC分类号: H01L29/76

    摘要: It is an object of the present invention to provide a nonvolatile semiconductor memory device which has superior writing characteristics and electric charge retention characteristics. In addition, it is an object of the present invention to provide a nonvolatile semiconductor memory device in which a writing voltage can be reduced. The nonvolatile semiconductor memory device includes a semiconductor region with a channel formation region formed between a pair of impurity regions which are formed to be apart from each other; and a first insulating layer, a charge accumulation layer, a second insulating layer, and a control gate are formed in a location which is a top layer portion of the semiconductor region and which roughly overlaps with the channel formation region. The charge accumulation layer is insulative and is formed as a layer in which electric charge can be trapped.

    摘要翻译: 本发明的目的是提供一种具有优异的写入特性和电荷保持特性的非易失性半导体存储器件。 此外,本发明的目的是提供一种可以减小写入电压的非易失性半导体存储器件。 非易失性半导体存储器件包括:半导体区域,其具有在形成为彼此分开的一对杂质区域之间形成的沟道形成区域; 并且在作为半导体区域的顶层部分并且与沟道形成区域大致重叠的位置处形成第一绝缘层,电荷累积层,第二绝缘层和控制栅极。 电荷蓄积层是绝缘的,并且形成为能够俘获电荷的层。

    Nonvolatile semiconductor memory device
    10.
    发明申请
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号:US20070221985A1

    公开(公告)日:2007-09-27

    申请号:US11723482

    申请日:2007-03-20

    IPC分类号: H01L29/788

    摘要: A nonvolatile semiconductor memory device which is superior in writing and charge holding properties, including a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions formed with an interval, and a first insulating layer, a floating gate, a second insulating layer, and a control gate over an upper layer portion of the semiconductor substrate. It is preferable that a band gap of a semiconductor material forming the floating gate be smaller than that of the semiconductor substrate. For example, it is preferable that the band gap of the semiconductor material forming the floating gate be smaller than that of the channel formation region in the semiconductor substrate by 0.1 eV or more. This is because, by decreasing the bottom energy level of a conduction band of the floating gate electrode to be lower than that of the channel formation region in the semiconductor substrate, carrier injecting and charge holding properties are improved.

    摘要翻译: 一种写入和电荷保持特性优异的非易失性半导体存储器件,包括在形成有间隔的一对杂质区域之间形成沟道形成区域的半导体衬底和第一绝缘层,浮置栅极,第二栅极 绝缘层和位于半导体衬底的上层部分上的控制栅极。 形成浮栅的半导体材料的带隙优选比半导体基板的带隙小。 例如,形成浮置栅极的半导体材料的带隙优选比半导体衬底中的沟道形成区域的带隙小0.1eV以上。 这是因为,通过将浮置栅电极的导带的底部能量水平降低到半导体衬底中的沟道形成区域的底部能级,能够提高载流子注入和电荷保持特性。