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公开(公告)号：US08399960B2
公开(公告)日：2013-03-19
申请号：US12920381
申请日：2009-02-20
IPC分类号： H01L27/08
CPC分类号： H01L27/0688 , H01L23/48 , H01L23/5227 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L25/0657 , H01L2224/05553 , H01L2224/48091 , H01L2224/49113 , H01L2225/06527 , H01L2924/00014 , H01L2924/14 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A plurality of semiconductor chips are juxtaposed, each having an electromagnetic induction coil disposed thereon. A signal is transmitted by way of electromagnetic induction between the electromagnetic induction coils disposed on a pair of adjacent semiconductor chips.
摘要翻译： 多个半导体芯片并置，每个具有布置在其上的电磁感应线圈。 在布置在一对相邻半导体芯片上的电磁感应线圈之间通过电磁感应传输信号。
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公开(公告)号：US20110006443A1
公开(公告)日：2011-01-13
申请号：US12920452
申请日：2009-02-19
IPC分类号： H01L23/48
CPC分类号： H01L23/645 , H01L23/5227 , H01L23/585 , H01L25/0655 , H01L25/0657 , H01L27/08 , H01L2224/16145 , H01L2225/06527 , H01L2225/06596
摘要： Disclosed is a semiconductor device composed of a plurality of semiconductor integrated circuits and a plurality of coils. During the production process of the semiconductor device, the plurality of coils are so arranged that the coil surfaces are generally perpendicular to the front surface of a chip of the semiconductor integrated circuits wherein metal films are laminated. A signal is transmitted between a pair of adjacent coils among the plurality of coils.
摘要翻译： 公开了由多个半导体集成电路和多个线圈组成的半导体器件。 在半导体器件的生产过程中，多个线圈被布置成使得线圈表面大致垂直于半导体集成电路的芯片的前表面，其中金属膜被层压。 信号在多个线圈中的一对相邻线圈之间传输。
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公开(公告)号：US20120233506A1
公开(公告)日：2012-09-13
申请号：US13510621
申请日：2010-11-26
申请人： Yoshio Kameda , Masayuki Mizuno
发明人： Yoshio Kameda , Masayuki Mizuno
IPC分类号： G06F11/28
CPC分类号： G06F11/1658 , G06F11/0793 , G06F11/1629 , G06F11/1641 , G06F11/165 , G06F11/1687 , G06F11/2236
摘要： A redundant computing system is composed of two systems: a first arithmetic processing unit (A-system) and a second arithmetic processing unit (B-system) having the same functions. A diagnosis control unit performs diagnosis of one system while the other system is performing arithmetic processing operation. The diagnosis control unit controls the input to the first and second arithmetic processing units by way of an input control unit according to the diagnosis operation, and an output control unit controls the output from the first and second arithmetic processing units according to the diagnosis result. After termination of the diagnosis, a value is copied from a storage unit of the system which has not been diagnosed to a storage unit of the system which has been diagnosed, and the redundant computing system resumes the redundant operation.
摘要翻译： 冗余计算系统由具有相同功能的第一算术处理单元（A系统）和第二算术处理单元（B系统）组成。 诊断控制单元执行一个系统的诊断，而另一个系统执行算术处理操作。 诊断控制单元根据诊断操作通过输入控制单元控制对第一和第二算术处理单元的输入，并且输出控制单元根据诊断结果控制来自第一和第二算术处理单元的输出。 在诊断结束后，从尚未被诊断的系统的存储单元复制到被诊断的系统的存储单元，并且冗余计算系统恢复冗余操作。
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公开(公告)号：US08862934B2
公开(公告)日：2014-10-14
申请号：US13510621
申请日：2010-11-26
申请人： Yoshio Kameda , Masayuki Mizuno
发明人： Yoshio Kameda , Masayuki Mizuno
CPC分类号： G06F11/1658 , G06F11/0793 , G06F11/1629 , G06F11/1641 , G06F11/165 , G06F11/1687 , G06F11/2236
摘要： A redundant computing system is composed of two systems: a first arithmetic processing unit (A-system) and a second arithmetic processing unit (B-system) having the same functions. A diagnosis control unit performs diagnosis of one system while the other system is performing arithmetic processing operation. The diagnosis control unit controls the input to the first and second arithmetic processing units by way of an input control unit according to the diagnosis operation, and an output control unit controls the output from the first and second arithmetic processing units according to the diagnosis result. After termination of the diagnosis, a value is copied from a storage unit of the system which has not been diagnosed to a storage unit of the system which has been diagnosed, and the redundant computing system resumes the redundant operation.
摘要翻译： 冗余计算系统由具有相同功能的第一算术处理单元（A系统）和第二算术处理单元（B系统）组成。 诊断控制单元执行一个系统的诊断，而另一个系统执行算术处理操作。 诊断控制单元根据诊断操作通过输入控制单元控制对第一和第二算术处理单元的输入，并且输出控制单元根据诊断结果控制来自第一和第二算术处理单元的输出。 在诊断结束后，从尚未被诊断的系统的存储单元复制到被诊断的系统的存储单元，并且冗余计算系统恢复冗余操作。
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5.发明授权公开(公告)号：US08441277B2
公开(公告)日：2013-05-14
申请号：US12810877
申请日：2008-12-16
申请人： Koichiro Noguchi , Yoshio Kameda , Koichi Nose , Masayuki Mizuno , Toshinobu Ono
发明人： Koichiro Noguchi , Yoshio Kameda , Koichi Nose , Masayuki Mizuno , Toshinobu Ono
IPC分类号： G01R31/26
CPC分类号： G01R31/31908
摘要： A semiconductor test apparatus, semiconductor device, and test method are provided that enable the realization of a high-speed delay test. Semiconductor test apparatuses (1a-1c) include: flip-flops (11) each provided with first input terminal SI, second input terminal D, mode terminal SE that accepts a mode signal indicating either a first mode or a second mode, clock terminal CK that accepts a clock signal, and output terminal Q, the flip-flops (11) selecting first input terminal SI when the mode signal indicates the first mode, selecting second input terminal D when the mode signal indicates the second mode, and holding information being received by the input terminal that was selected based on the mode signal in synchronization with the clock signal and supplying as output from output terminal Q; and hold unit 12 that holds a set value and that provides the set value to first input terminal SI.
摘要翻译： 提供了能够实现高速延迟测试的半导体测试装置，半导体器件和测试方法。 半导体测试装置（1a-1c）包括：各自配置有第一输入端子SI的触发器（11），第二输入端子D，接受指示第一模式或第二模式的模式信号的模式端子SE，时钟端子CK 接收时钟信号和输出端子Q，当模式信号指示第一模式时，触发器（11）选择第一输入端子SI，当模式信号指示第二模式时选择第二输入端子D，并且保持信息为 由与输入端Q同步地基于模式信号选择的输入端接收，并从输出端Q输出; 并且保持单元12保持设定值，并将设定值提供给第一输入端子SI。
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公开(公告)号：US08330254B2
公开(公告)日：2012-12-11
申请号：US12647639
申请日：2009-12-28
申请人： Masayuki Furumiya , Hiroaki Ohkubo , Fuyuki Okamoto , Masayuki Mizuno , Koichi Nose , Yoshihiro Nakagawa , Yoshio Kameda
发明人： Masayuki Furumiya , Hiroaki Ohkubo , Fuyuki Okamoto , Masayuki Mizuno , Koichi Nose , Yoshihiro Nakagawa , Yoshio Kameda
IPC分类号： H01L23/544
CPC分类号： H01L23/48 , G01R31/2884 , G01R31/3025 , G01R31/31721 , H01L22/32 , H01L23/50 , H01L23/5286 , H01L23/544 , H01L24/06 , H01L2223/5446 , H01L2924/01029
摘要： A semiconductor device includes a semiconductor wafer in which semiconductor chip forming regions and a scribe region located between the semiconductor chip forming regions are formed, a plurality of semiconductor chip circuit portions provided over the semiconductor wafer, a plurality of first conductive layers, provided in each of the semiconductor chip forming regions, which is electrically connected to each of the circuit portions, and a first connecting portion that electrically connects the first conductive layers to each other across a portion of the scribe region. An external power supply or grounding pad is connected to any one of the first conductive layer and the first connecting portion. The semiconductor device includes a communication portion, connected to the circuit portion, which performs communication with the outside by capacitive coupling or inductive coupling.
摘要翻译： 一种半导体器件包括其半导体芯片形成区域和位于半导体芯片形成区域之间的划线区域形成的半导体晶片，设置在半导体晶片上的多个半导体芯片电路部分，设置在每个半导体芯片形成区域中的多个第一导电层 电连接到每个电路部分的半导体芯片形成区域以及跨越划线区域的一部分将第一导电层彼此电连接的第一连接部分。 外部电源或接地焊盘连接到第一导电层和第一连接部分中的任一个。 半导体器件包括连接到电路部分的通信部分，其通过电容耦合或电感耦合与外部进行通信。
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公开(公告)号：US20110260747A1
公开(公告)日：2011-10-27
申请号：US13139609
申请日：2009-12-22
CPC分类号： G01R31/2884 , G01R31/3012
摘要： A semiconductor device (1) includes a semiconductor wafer (11) on which a plurality of semiconductor chip forming regions (1A) is formed, a circuit section (12) which is provided within each of the semiconductor chip forming regions (1A) of the semiconductor wafer (11), a control circuit section (14), provided within each of the semiconductor chip forming regions (1A) and connected to the circuit section (12), that controls electric power supplied to the circuit section (12), a power supply line (18) connected to the plurality of control circuit section (14), and a reference power line (17) connected to the plurality of control circuit section (14). In each of the control circuit sections (14), a voltage of electric power supplied from the power supply line (18) is controlled on the basis of a reference voltage from the reference power line (17).
摘要翻译： 半导体器件（1）包括其上形成有多个半导体芯片形成区域（1A）的半导体晶片（11），设置在所述半导体芯片形成区域（1A）的每一个内的电路部分（12） 半导体晶片（11），设置在每个半导体芯片形成区域（1A）内并连接到电路部分（12））的控制电路部分（14），其控制供应到电路部分（12）的电力， 连接到多个控制电路部分（14）的电源线（18）和连接到多个控制电路部分（14）的参考电力线（17）。 在每个控制电路部分（14）中，基于来自参考电力线（17）的参考电压来控制从电源线（18）供应的电力的电压。
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公开(公告)号：US08513970B2
公开(公告)日：2013-08-20
申请号：US13139609
申请日：2009-12-22
IPC分类号： G01R31/02
CPC分类号： G01R31/2884 , G01R31/3012
摘要： A semiconductor device (1) includes a semiconductor wafer (11) on which a plurality of semiconductor chip forming regions (1A) is formed, a circuit section (12) which is provided within each of the semiconductor chip forming regions (1A) of the semiconductor wafer (11), a control circuit section (14), provided within each of the semiconductor chip forming regions (1A) and connected to the circuit section (12), that controls electric power supplied to the circuit section (12), a power supply line (18) connected to the plurality of control circuit section (14), and a reference power line (17) connected to the plurality of control circuit section (14). In each of the control circuit sections (14), a voltage of electric power supplied from the power supply line (18) is controlled on the basis of a reference voltage from the reference power line (17).
摘要翻译： 半导体器件（1）包括其上形成有多个半导体芯片形成区域（1A）的半导体晶片（11），设置在所述半导体芯片形成区域（1A）的每一个内的电路部分（12） 半导体晶片（11），设置在每个半导体芯片形成区域（1A）内并连接到电路部分（12））的控制电路部分（14），其控制供应到电路部分（12）的电力， 连接到多个控制电路部分（14）的电源线（18）和连接到多个控制电路部分（14）的参考电力线（17）。 在每个控制电路部分（14）中，基于来自参考电力线（17）的参考电压来控制从电源线（18）供应的电力的电压。
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公开(公告)号：US20110012228A1
公开(公告)日：2011-01-20
申请号：US12920381
申请日：2009-02-20
IPC分类号： H01L29/86
CPC分类号： H01L27/0688 , H01L23/48 , H01L23/5227 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L25/0657 , H01L2224/05553 , H01L2224/48091 , H01L2224/49113 , H01L2225/06527 , H01L2924/00014 , H01L2924/14 , H01L2924/3025 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A plurality of semiconductor chips are juxtaposed, each having an electromagnetic induction coil disposed thereon. A signal is transmitted by way of electromagnetic induction between the electromagnetic induction coils disposed on a pair of adjacent semiconductor chips.
摘要翻译： 多个半导体芯片并置，每个具有布置在其上的电磁感应线圈。 在布置在一对相邻半导体芯片上的电磁感应线圈之间通过电磁感应传输信号。
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10.发明申请公开(公告)号：US20100283497A1
公开(公告)日：2010-11-11
申请号：US12810877
申请日：2008-12-16
申请人： Koichiro Noguchi , Yoshio Kameda , Koichi Nose , Masayuki Mizuno , Toshinobu Ono
发明人： Koichiro Noguchi , Yoshio Kameda , Koichi Nose , Masayuki Mizuno , Toshinobu Ono
IPC分类号： G01R31/26
CPC分类号： G01R31/31908
摘要： A semiconductor test apparatus, semiconductor device, and test method are provided that enable the realization of a high-speed delay test. Semiconductor test apparatuses (1a-1c) include: flip-flops (11) each provided with first input terminal SI, second input terminal D, mode terminal SE that accepts a mode signal indicating either a first mode or a second mode, clock terminal CK that accepts a clock signal, and output terminal Q, the flip-flops (11) selecting first input terminal SI when the mode signal indicates the first mode, selecting second input terminal D when the mode signal indicates the second mode, and holding information being received by the input terminal that was selected based on the mode signal in synchronization with the clock signal and supplying as output from output terminal Q; and hold unit 12 that holds a set value and that provides the set value to first input terminal SI.
摘要翻译： 提供了能够实现高速延迟测试的半导体测试装置，半导体器件和测试方法。 半导体测试装置（1a-1c）包括：各自配置有第一输入端子SI的触发器（11），第二输入端子D，接受指示第一模式或第二模式的模式信号的模式端子SE，时钟端子CK 接收时钟信号和输出端子Q，当模式信号指示第一模式时，触发器（11）选择第一输入端子SI，当模式信号指示第二模式时选择第二输入端子D，并且保持信息为 由与输入端Q同步地基于模式信号选择的输入端接收，并从输出端Q输出; 并且保持单元12保持设定值，并将设定值提供给第一输入端子SI。
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