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    Semiconductor storage device and method for manufacturing same
    1.
    发明授权
    Semiconductor storage device and method for manufacturing same 有权
    半导体存储装置及其制造方法

    公开(公告)号：US08563961B2

    公开(公告)日：2013-10-22

    申请号：US13515435

    申请日：2010-12-13

    申请人： Yoshitaka Sasago ,  Akio Shima ,  Satoru Hanzawa ,  Takashi Kobayashi ,  Masaharu Kinoshita ,  Norikastsu Takaura

    发明人： Yoshitaka Sasago ,  Akio Shima ,  Satoru Hanzawa ,  Takashi Kobayashi ,  Masaharu Kinoshita ,  Norikastsu Takaura

    IPC分类号： H01L47/00

    CPC分类号： H01L45/1666 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

    摘要： Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line (2) which is provided above the substrate; a first laminated body, which is disposed above the first word line (2), and which has the N+1 (N≧1) number of first inter-gate insulating layers (11-15) and the N number of first semiconductor layers (21p-24p) alternately laminated in the height direction of the substrate; a first bit line (3), which extends in the direction that intersects the first word line (2), and which is disposed above the laminated body; a first gate insulating layer (9) which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (11-15) and those of the N number of the first semiconductor layers (21p-24p); a first channel layer (8p) which is provided on the side surface of the first gate insulating layer (9); and a first variable resistance material layer (7) which is provided on the side surface of the first channel layer. The first variable material layer (7) is in a region where the first word line (2) and the first bit line (3) intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.

    摘要翻译： 公开了一种半导体存储装置和用于制造半导体存储装置的方法，由此降低了使用可变电阻材料的存储器的位成本。 半导体存储装置具有：基板; 设置在基板上方的第一字线（2） 第一层叠体，其设置在第一字线（2）的上方，并且具有N + 1（N> = 1）个第一栅极间绝缘层（11-15）和N个第一半导体 层（21p-24p）在基板的高度方向交替层叠; 第一位线（3），其在与所述第一字线（2）相交的方向上延伸，并且位于所述层叠体的上方; 设置在N + 1个第一栅极绝缘层（11-15）的侧表面和N个第一半导体层（21p-24p）的侧表面上的第一栅极绝缘层（9） ; 设置在第一栅极绝缘层（9）的侧面上的第一沟道层（8p）; 以及设置在第一沟道层的侧表面上的第一可变电阻材料层（7）。 第一可变材料层（7）在第一字线（2）和第一位线（3）彼此相交的区域中。 此外，使用多晶硅二极管（PD）作为选择元件。

    SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME
    2.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING SAME 有权
    半导体存储器件及其制造方法

    公开(公告)号：US20120248399A1

    公开(公告)日：2012-10-04

    申请号：US13515435

    申请日：2010-12-13

    申请人： Yoshitaka Sasago ,  Akio Shima ,  Satoru Hanzawa ,  Takashi Kobayashi ,  Masaharu Kinoshita ,  Norikastsu Takaura

    发明人： Yoshitaka Sasago ,  Akio Shima ,  Satoru Hanzawa ,  Takashi Kobayashi ,  Masaharu Kinoshita ,  Norikastsu Takaura

    IPC分类号： H01L27/24

    CPC分类号： H01L45/1666 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

    摘要： Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line (2) which is provided above the substrate; a first laminated body, which is disposed above the first word line (2), and which has the N+1 (N≧1) number of first inter-gate insulating layers (11-15) and the N number of first semiconductor layers (21p-24p) alternately laminated in the height direction of the substrate; a first bit line (3), which extends in the direction that intersects the first word line (2), and which is disposed above the laminated body; a first gate insulating layer (9) which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (11-15) and those of the N number of the first semiconductor layers (21p-24p); a first channel layer (8p) which is provided on the side surface of the first gate insulating layer (9); and a first variable resistance material layer (7) which is provided on the side surface of the first channel layer. The first variable material layer (7) is in a region where the first word line (2) and the first bit line (3) intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.

    摘要翻译： 公开了一种半导体存储装置和用于制造半导体存储装置的方法，由此降低了使用可变电阻材料的存储器的位成本。 半导体存储装置具有：基板; 设置在基板上方的第一字线（2） 第一层叠体，其设置在第一字线（2）的上方，并且具有N + 1（N≥1）个第一栅极间绝缘层（11-15）和N个第一半导体层 （21p-24p）在基板的高度方向上交替层叠; 第一位线（3），其在与所述第一字线（2）相交的方向上延伸，并且位于所述层叠体的上方; 设置在N + 1个第一栅极绝缘层（11-15）的侧表面和N个第一半导体层（21p-24p）的侧表面上的第一栅极绝缘层（9） ; 设置在第一栅极绝缘层（9）的侧面上的第一沟道层（8p）; 以及设置在第一沟道层的侧表面上的第一可变电阻材料层（7）。 第一可变材料层（7）在第一字线（2）和第一位线（3）彼此相交的区域中。 此外，使用多晶硅二极管（PD）作为选择元件。

    Semiconductor memory device
    9.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08772746B2

    公开(公告)日：2014-07-08

    申请号：US13349653

    申请日：2012-01-13

    申请人： Masaharu Kinoshita ,  Yoshitaka Sasago ,  Takashi Kobayashi

    发明人： Masaharu Kinoshita ,  Yoshitaka Sasago ,  Takashi Kobayashi

    IPC分类号： H01L47/00

    CPC分类号： H01L45/06 ,  H01L27/2454 ,  H01L27/2472 ,  H01L45/144 ,  H01L45/1675

    摘要： A semiconductor memory device in which the cell area can be decreased and the minimum feature size is not restricted by the thickness of the material forming the memory cell. In a semiconductor memory device, a gate insulating film, a channel extending in a direction X, and a resistance change element extending in the direction X are formed successively above multiple word lines extending in a direction Y, and a portion of the channel and a portion of the resistance change element are disposed above each of the plurality of the word lines. Such configuration can decrease the cell area and ensure the degree of design freedom.

    摘要翻译： 可以减小单元面积并且最小特征尺寸不受形成存储单元的材料的厚度的半导体存储器件。 在半导体存储器件中，连续地沿着Y方向延伸的多个字线形成栅极绝缘膜，沿X方向延伸的沟道和沿X方向延伸的电阻变化元件，并且沟道的一部分和 电阻变化元件的一部分设置在多条字线的上方。 这样的配置可以减小单元面积并确保设计自由度。

    Non-volatile memory device
    10.
    发明授权
    Non-volatile memory device 有权
    非易失性存储器件

    公开(公告)号：US08642988B2

    公开(公告)日：2014-02-04

    申请号：US13588112

    申请日：2012-08-17

    申请人： Masaharu Kinoshita ,  Yoshitaka Sasago ,  Takashi Kobayashi ,  Hiroyuki Minemura

    发明人： Masaharu Kinoshita ,  Yoshitaka Sasago ,  Takashi Kobayashi ,  Hiroyuki Minemura

    IPC分类号： H01L29/02

    CPC分类号： H01L45/144 ,  G11C13/0004 ,  G11C2213/71 ,  G11C2213/74 ,  G11C2213/75 ,  G11C2213/78 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06

    摘要： A non-volatile memory device includes: a first line extending along a main surface of a substrate; a stack provided above the first line; a second line formed above the stack; a select element provided where the first and second lines intersect, the select element adapted to pass current in a direction perpendicular to the main surface; a second insulator film provided along a side surface of the stack; a channel layer provided along the second insulator film; an adhesion layer provided along the channel layer; and a variable resistance material layer provided along the adhesion layer, wherein the first and second lines are electrically connected via the select element and channel layer, a contact resistance via the adhesion layer between the channel layer and variable resistance material layer is low, and a resistance of the adhesion layer is high with respect to an extending direction of the channel layer.

    摘要翻译： 非易失性存储器件包括：沿衬底的主表面延伸的第一线; 提供在第一行之上的堆栈; 在堆叠之上形成第二线; 设置在所述第一和第二线相交的选择元件，所述选择元件适于在垂直于所述主表面的方向上传递电流; 沿着所述堆叠的侧表面设置的第二绝缘膜; 沿所述第二绝缘膜设置的沟道层; 沿着沟道层提供的粘合层; 以及沿着粘合层设置的可变电阻材料层，其中第一和第二线经由选择元件和沟道层电连接，通过沟道层和可变电阻材料层之间的粘合层的接触电阻低，并且 粘合层的电阻相对于沟道层的延伸方向高。