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    Semiconductor device manufacturing device
    5.
    发明授权
    Semiconductor device manufacturing device 失效
    半导体装置制造装置

    公开(公告)号：US07534721B2

    公开(公告)日：2009-05-19

    申请号：US11863403

    申请日：2007-09-28

    申请人： Ryuichi Kanamura

    发明人： Ryuichi Kanamura

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76835 ,  H01L21/76811 ,  H01L21/76813

    摘要： A process for production of a semiconductor device having a multi-layer wiring of dual damascene structure in a low-dielectric constant interlayer insulating film. The process consists of the following steps. A first insulating film and a second insulating film are formed. A first to third mask forming layers are formed. The third mask forming layer is patterned so as to form the third mask for the wiring groove pattern. A resist mask of the connecting hole pattern is formed on the second mask forming layer including the third mask. The third mask and the second and first mask forming layers are etched, and the second insulating film is etched. The second mask of the wiring groove pattern is formed by using the third mask, and the connecting hole is made to the middle of the first insulating film. The first mask forming layer is etched by using the second mask, and the first mask of the wiring groove pattern is formed, and the first insulating film remaining at the bottom of the connecting hole is etched so as to make the connecting hole. The wiring groove is formed in the second insulating film by using the first or second mask.

    摘要翻译： 一种在低介电常数层间绝缘膜中制造具有双镶嵌结构的多层布线的半导体器件的工艺。 该过程包括以下步骤。 形成第一绝缘膜和第二绝缘膜。 形成第一至第三掩模形成层。 图案化第三掩模形成层以形成用于布线槽图案的第三掩模。 在包括第三掩模的第二掩模形成层上形成连接孔图案的抗蚀剂掩模。 蚀刻第三掩模和第二和第一掩模形成层，并蚀刻第二绝缘膜。 通过使用第三掩模形成布线槽图案的第二掩模，并且连接孔形成在第一绝缘膜的中间。 通过使用第二掩模蚀刻第一掩模形成层，并且形成布线槽图案的第一掩模，并且蚀刻留在连接孔底部的第一绝缘膜，以便形成连接孔。 通过使用第一或第二掩模在第二绝缘膜中形成布线槽。

    Production method of semiconductor device
    6.
    发明授权
    Production method of semiconductor device 失效
    半导体器件的制造方法

    公开(公告)号：US07119007B2

    公开(公告)日：2006-10-10

    申请号：US11097137

    申请日：2005-04-04

    申请人： Ryuichi Kanamura

    发明人： Ryuichi Kanamura

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76835 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76825 ,  H01L21/76829 ,  Y10S438/942

    摘要： The method includes forming on an underlayer wiring a first insulating film, a second insulating, and first mask forming layer; forming a first resist mask having an inverted pattern of wiring Wenches for the upper wiring; etching the first mask forming layer through the first resist mask, thereby forming in the first mask forming layer a concave part conforming to the inverted pattern of wiring tenches for the upper wiring, forming on the first mask forming layer a second mask forming layer, thereby filling the concave part with the second mask forming layer; selectively removing the second mask forming layer on the region in which the wiring trench is formed, thereby forming the second mask having the wiring trench pattern; forming on the first mask forming layer a second resist mask having an opening pattern of the via holes; etching the first mask forming layer and the second insulating film through the second resist mask, thereby forming the via holes.

    摘要翻译： 该方法包括在下层布线上形成第一绝缘膜，第二绝缘和第一掩模形成层; 形成具有反向图案布线的第一抗蚀剂掩模，用于上布线; 通过第一抗蚀剂掩模蚀刻第一掩模形成层，从而在第一掩模形成层中形成符合用于上布线的布线桥的倒置图案的凹部，在第一掩模形成层上形成第二掩模形成层，由此 用第二掩模形成层填充凹部; 在形成布线沟槽的区域上选择性地去除第二掩模形成层，从而形成具有布线沟槽图案的第二掩模; 在所述第一掩模形成层上形成具有所述通孔的开口图案的第二抗蚀剂掩模; 通过第二抗蚀剂掩模蚀刻第一掩模形成层和第二绝缘膜，从而形成通孔。

    Resist stripping composition and method of producing semiconductor device using the same
    7.
    发明授权
    Resist stripping composition and method of producing semiconductor device using the same 有权
    抗剥离组合物及使用其制造半导体器件的方法

    公开(公告)号：US07087563B2

    公开(公告)日：2006-08-08

    申请号：US10467354

    申请日：2002-12-04

    申请人： Hayato Iwamoto ,  Ryuichi Kanamura ,  Ai Endou ,  Tomoko Suzuki ,  Toshitaka Hiraga

    发明人： Hayato Iwamoto ,  Ryuichi Kanamura ,  Ai Endou ,  Tomoko Suzuki ,  Toshitaka Hiraga

    IPC分类号： C11D7/50

    CPC分类号： G03F7/425 ,  G03F7/422 ,  G03F7/423 ,  H01L21/02052 ,  H01L21/76802

    摘要： A resist stripping composition capable of reliably stripping off resist residue or polymer residue and keeping damage to the interconnects to a minimum and a method of producing a semiconductor device using the same, where the resist stripping composition comprises a salt of hydrofluoric acid and a base not including a metal, an organic solvent, a sugar alcohol such as xylitol, and water and has a hydrogen ion concentration of at least 8. The method of production of a semiconductor device comprises dry etching a metal layer or a semiconductor layer on a semiconductor substrate to form an interconnect layer having a predetermined pattern or forming an insulation layer on a semiconductor substrate formed with an interconnect layer and dry etching this to a predetermined pattern, then performing chemical treatment using a resist stripping composition comprising a salt of hydrofluoric acid and a base not including a metal, an organic solvent, a sugar alcohol such as xylitol, and water and having a hydrogen ion concentration of at least 8.

    摘要翻译： 能够可靠地剥离抗蚀剂残留物或聚合物残余物并将互连件的损伤保持最小化的抗蚀剂剥离组合物和使用其的制造半导体器件的方法，其中抗蚀剂剥离组合物包含氢氟酸盐和不含碱 包括金属，有机溶剂，糖醇如木糖醇和水，并且具有至少8的氢离子浓度。半导体器件的制造方法包括在半导体衬底上干蚀刻金属层或半导体层 以形成具有预定图案的互连层或在形成有互连层的半导体衬底上形成绝缘层，并将其干蚀刻至预定图案，然后使用包含氢氟酸盐和碱的抗蚀剂剥离组合物进行化学处理 不包括金属，有机溶剂，糖醇如木糖醇，以及水和 氢离子浓度至少为8。

    Method of manufacturing semiconductor device
    8.
    发明授权
    Method of manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US07176120B2

    公开(公告)日：2007-02-13

    申请号：US11175790

    申请日：2005-07-06

    申请人： Ryuichi Kanamura

    发明人： Ryuichi Kanamura

    IPC分类号： H01L29/06

    CPC分类号： H01L21/76835 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816

    摘要： A method of manufacturing a semiconductor device, including the steps of: forming first and second insulation films on a substrate; sequentially forming an organic sacrificing layer and first and second mask layers thereon; forming a wiring groove pattern in the second mask layer; forming a connection hole pattern for forming connection holes in the second and first mask layers and the organic sacrificing layer; forming a wiring groove pattern in the first mask layer and the organic sacrificing layer and forming the connection holes in the second insulation film, by etching conducted by use of the second and first mask layers as an etching mask; and forming the wiring grooves in the second insulation film and forming the connection holes in the second and first insulation films, by use of the first mask layer and the organic sacrificing layer as a mask.

    摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在衬底上形成第一和第二绝缘膜; 在其上依次形成有机牺牲层和第一和第二掩模层; 在所述第二掩模层中形成布线槽图案; 形成用于在第二和第一掩模层和有机牺牲层中形成连接孔的连接孔图案; 在所述第一掩模层和所述有机牺牲层中形成布线槽图案，并且通过使用所述第二掩模层和所述第一掩模层进行的蚀刻作为蚀刻掩模，在所述第二绝缘膜中形成所述连接孔; 以及在所述第二绝缘膜中形成所述布线槽并且通过使用所述第一掩模层和所述有机牺牲层作为掩模在所述第二绝缘膜和所述第一绝缘膜中形成所述连接孔。

    Semiconductor device
    9.
    发明申请
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US20060192286A1

    公开(公告)日：2006-08-31

    申请号：US11341067

    申请日：2006-01-27

    申请人： Ryuichi Kanamura

    发明人： Ryuichi Kanamura

    IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

    CPC分类号： H01L21/76835 ,  H01L21/76808 ,  H01L21/76811 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed herein is a semiconductor device having a multi-layer wiring structure includes a plurality of wiring layers laminated on a substrate, the wiring layers each including a buried wiring and a via formed by filling with a conductive material the inside of a wiring trench formed on the face side of a layer insulation film and a contact hole provided at a bottom portion of the wiring trench. The layer insulation films constituting the plurality of wiring layers are so configured that the layer insulation films are changed in the magnitude of mechanical strength alternately on a wiring layer basis in the lamination direction of the wiring layers.

    摘要翻译： 本发明公开了具有层叠在基板上的多层布线层的多层布线结构的半导体装置，所述布线层各自包括掩埋布线和通过在导电材料上填充形成的布线沟槽的内部而形成的通孔， 层绝缘膜的表面侧和设置在布线沟槽的底部的接触孔。 构成多个布线层的层间绝缘膜被构造为使层间绝缘膜在布线层的层叠方向上基于布线层交替地改变机械强度的大小。

    Method of forming interconnection
    10.
    发明授权
    Method of forming interconnection 失效
    形成互连的方法

    公开(公告)号：US5723362A

    公开(公告)日：1998-03-03

    申请号：US680541

    申请日：1996-07-09

    申请人： Hajime Inoue ,  Ryuichi Kanamura

    发明人： Hajime Inoue ,  Ryuichi Kanamura

    IPC分类号： H01L21/28 ,  H01L21/203 ,  H01L21/285 ,  H01L21/768 ,  H01L21/443

    CPC分类号： H01L21/76856 ,  H01L21/28568 ,  H01L21/76843 ,  H01L21/76855

    摘要： A method of forming an interconnection in a contact hole having a high aspect ratio, which is capable of certainly forming a barrier layer metal layer and burying a blanket W film in the contact hole without generation of any void. A Ti film is deposited in a contact hole by sputtering using a sputter system having a collimator plate and an oxidation preventive TiN thin film is deposited thereon by reactive sputtering using the same sputter system having the collimator plate. Next, a titanium silicide layer is formed by a first heat-treatment and a TiN film is formed by a second heat-treatment. Finally, a blanket W film is deposited by CVD to be buried in the contact hole.

    摘要翻译： 在具有高纵横比的接触孔中形成互连的方法，其能够可靠地形成阻挡层金属层并且在接触孔中埋入覆盖W膜而不产生任何空隙。 使用具有准直板的溅射系统通过溅射将Ti膜沉积在接触孔中，并通过使用具有准直板的相同溅射系统通过反应溅射在其上沉积防氧化TiN薄膜。 接下来，通过第一热处理形成硅化钛层，通过第二热处理形成TiN膜。 最后，通过CVD沉积覆盖W膜以埋入接触孔中。