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    SEMICONDUCTOR MEMORY DEVICE
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开
    半导体存储器件

    公开(公告)号：US20100044773A1

    公开(公告)日：2010-02-25

    申请号：US12495093

    申请日：2009-06-30

    申请人： Yoshiyuki Ishigaki ,  Naoki Tsuji ,  Hisakazu Otoi ,  Hiroki Mukai ,  Yuichi Kunori

    发明人： Yoshiyuki Ishigaki ,  Naoki Tsuji ,  Hisakazu Otoi ,  Hiroki Mukai ,  Yuichi Kunori

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11521 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/7881

    摘要： To provide a semiconductor memory device having an improved write efficiency because deterioration of a gate insulating film is suppressed.An element formation region is formed in a region of a semiconductor substrate sandwiched between element isolation regions. In the element isolation regions, a silicon oxide film is filled in a trench having a predetermined depth. An erase gate electrode is formed in the element isolation region while being buried in the silicon oxide film. Over the element formation region, floating gate electrodes are formed via a gate oxide film and control gate electrodes are formed over the floating gate electrodes via an ONO film. Two adjacent floating gate electrodes have therebetween an insulating film formed to cover the erase gate electrode.

    摘要翻译： 提供一种由于栅极绝缘膜的劣化被抑制而具有提高的写入效率的半导体存储器件。 元件形成区域形成在夹在元件隔离区域之间的半导体衬底的区域中。 在元件隔离区域中，氧化硅膜填充在具有预定深度的沟槽中。 在元件隔离区域中形成擦除栅电极，同时埋入氧化硅膜中。 在元件形成区域上，通过栅极氧化膜形成浮栅，并且通过ONO膜在浮栅上形成控制栅电极。 两个相邻的浮栅电极之间形成有覆盖擦除栅电极的绝缘膜。

    Semiconductor device having memory cells and method of manufacturing the same
    4.
    发明授权
    Semiconductor device having memory cells and method of manufacturing the same 失效
    具有存储单元的半导体器件及其制造方法

    公开(公告)号：US06271569B1

    公开(公告)日：2001-08-07

    申请号：US09008594

    申请日：1998-01-16

    申请人： Yoshiyuki Ishigaki ,  Hiroki Honda

    发明人： Yoshiyuki Ishigaki ,  Hiroki Honda

    IPC分类号： H01L2976

    CPC分类号： H01L27/11 ,  H01L27/1112 ,  Y10S257/903 ,  Y10S257/904

    摘要： According to a semiconductor device and a method of manufacturing the same, a storage node has an increased capacity, and a resistance against soft error is improved. A GND interconnection is formed on a first interconnection layer including storage node portions with a dielectric film therebetween. Thereby, the storage node portions, the dielectric film, and the GND interconnection form a capacity element of the storage node portion. The first interconnection layer is arranged symmetrically around the center of the memory cell, and a plurality of memory cells having the same layout and neighboring to each other are arranged along the word lines.

    摘要翻译： 根据半导体器件及其制造方法，存储节点具有增加的容量，并且提高了对软错误的抵抗力。 GND互连形成在包括其间具有介电膜的存储节点部分的第一互连层上。 由此，存储节点部分，电介质膜和GND互连构成存储节点部分的电容元件。 第一互连层围绕存储单元的中心对称布置，并且沿着字线布置具有相同布局并且彼此相邻的多个存储单元。

    SRAM semiconductor device
    5.
    发明授权
    SRAM semiconductor device 失效
    SRAM半导体器件

    公开(公告)号：US5619056A

    公开(公告)日：1997-04-08

    申请号：US693497

    申请日：1996-08-07

    申请人： Hirotada Kuriyama ,  Masahiro Ishida ,  Yoshiyuki Ishigaki

    发明人： Hirotada Kuriyama ,  Masahiro Ishida ,  Yoshiyuki Ishigaki

    IPC分类号： H01L27/11 ,  H01L21/8244 ,  H01L29/76 ,  H01L27/108

    CPC分类号： H01L27/1108 ,  H01L27/11 ,  Y10S257/903

    摘要： The present invention provides an improved static random access memory which can be manufactured into values as designed by photolithography. Second direct contract for connecting active region and ground line for first and second memory cells is provided at a boundary between the first memory cell and second memory cell. Second direct contact is divided into a plurality of portions.

    摘要翻译： 本发明提供一种改进的静态随机存取存储器，其可以被制造成通过光刻设计的值。 在第一存储单元和第二存储单元之间的边界处提供用于连接用于第一和第二存储单元的有源区和接地线的第二直接合同。 第二直接接触被分成多个部分。

    Semiconductor device and method of manufacturing thereof
    6.
    发明授权
    Semiconductor device and method of manufacturing thereof 失效
    半导体装置及其制造方法

    公开(公告)号：US5350939A

    公开(公告)日：1994-09-27

    申请号：US37141

    申请日：1993-03-25

    申请人： Hiroki Honda ,  Kimiharu Uga ,  Masahiro Ishida ,  Yoshiyuki Ishigaki

    发明人： Hiroki Honda ,  Kimiharu Uga ,  Masahiro Ishida ,  Yoshiyuki Ishigaki

    IPC分类号： H01L21/74 ,  H01L21/76 ,  H01L27/06 ,  H01L27/08 ,  H01L27/02

    CPC分类号： H01L27/0623

    摘要： An n.sup.- epitaxial layer 4 is formed on the top face of a p type semiconductor substrate 1. A p.sup.+ buried layer 20 is formed by implanting ions in the region extending over the p type semiconductor substrate 1 and the n.sup.- epitaxial layer 4. A p.sup.+ channel stop is formed in the upper layer of the p.sup.+ buried layer 20 by ion implantation. A p well is formed extending from the upper layer of the p.sup.+ channel stop to the top face of the n.sup.- epitaxial layer. An n channel MOS type field effect transistor 200 is formed in the p well 22. It is possible to reliably isolate an element from an adjacent element thereto because of the structure.

    摘要翻译： n型外延层4形成在p型半导体衬底1的顶面上。通过在p型半导体衬底1和n外延层4上延伸的区域中注入离子形成p +埋层20。 通过离子注入在p +掩埋层20的上层形成沟道阻挡层。 形成从p +沟道阻挡层的上层延伸到n外延层的顶面的p阱。 在p阱22中形成n沟道MOS型场效应晶体管200.由于结构，可以将元件与相邻元件可靠地隔离。

    Semiconductor device including complementary insulating gate field effect transistors and bipolar transistors in semiconductor substrate
    7.
    发明授权
    Semiconductor device including complementary insulating gate field effect transistors and bipolar transistors in semiconductor substrate 失效
    半导体器件包括补充绝缘栅场效应晶体管和双极晶体管在半导体衬底

    公开(公告)号：US5245209A

    公开(公告)日：1993-09-14

    申请号：US798096

    申请日：1991-11-27

    申请人： Yoshiyuki Ishigaki

    发明人： Yoshiyuki Ishigaki

    IPC分类号： H01L21/8249 ,  H01L21/74 ,  H01L27/06 ,  H01L27/092

    CPC分类号： H01L21/74 ,  H01L27/0623 ,  H01L27/0921

    摘要： The impurity concentration of an n.sup.+ buried layer 51a in the region for forming a p channel MOS transistor 23 is higher than the impurity concentration of an n.sup.+ buried layer 3a in the region for forming an npn bipolar transistor 21. N.sup.+ buried layers 3a and 51a are formed on a p type silicon substrate 1. An n.sup.- well region 10 is formed as a region for forming npn bipolar transistor 21 on n.sup.+ buried layer 3a. An n well region 12 is formed as a region for forming p channel MOS transistor 23 on n.sup.+ buried layer 51a. While the performance of npn bipolar transistor 21 is maintained, the performance of a CMOS transistor formed of an n channel MOS transistor 22 and p channel MOS transistor 23 is improved. In a Bi-CMOS semiconductor device, the performance of a bipolar transistor portion is maintained, while preventing the formation of a punch through and improving the latch up tolerance of a CMOS transistor portion.

    摘要翻译： 用于形成p沟道MOS晶体管23的区域中的n +掩埋层51a的杂质浓度高于用于形成npn双极晶体管21的区域中的n +掩埋层3a的杂质浓度。形成N +掩埋层3a和51a 在p型硅衬底1上形成n阱区10作为在n +掩埋层3a上形成npn双极晶体管21的区域。 n阱区12形成为在n +掩埋层51a上形成p沟道MOS晶体管23的区域。 在保持npn双极晶体管21的性能的同时，提高了由n沟道MOS晶体管22和p沟道MOS晶体管23构成的​​CMOS晶体管的性能。 在Bi-CMOS半导体器件中，保持双极性晶体管部分的性能，同时防止形成穿孔并提高CMOS晶体管部分的锁存容差。

    Semiconductor device and method of manufacturing the same
    8.
    发明申请
    Semiconductor device and method of manufacturing the same 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20060194390A1

    公开(公告)日：2006-08-31

    申请号：US11355177

    申请日：2006-02-16

    申请人： Yutaka Imai ,  Yoshiyuki Ishigaki

    发明人： Yutaka Imai ,  Yoshiyuki Ishigaki

    IPC分类号： H01L21/336 ,  H01L21/44 ,  H01L23/48

    CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes an interlayer insulation film including an air gap between portions of adjacent wiring layers or isolation pattern layers or both that are distanced from each other by thinning a layered structure of each of the wiring layers or the isolation pattern layers or both selectively from a top layer to a substrate so that the portions of the wiring layers or the isolation pattern layers or both are distanced from each other.

    摘要翻译： 半导体器件包括层间绝缘膜，该层间绝缘膜包括相邻布线层的部分之间的气隙或隔离图案层，或者通过使每个布线层或隔离图案层的层叠结构变薄或两者选择性地彼此分开， 顶层到基板，使得布线层或隔离图案层的一部分或两者彼此间隔开。

    Semiconductor device and a method of manufacturing the same
    9.
    发明申请
    Semiconductor device and a method of manufacturing the same 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20060125024A1

    公开(公告)日：2006-06-15

    申请号：US11297501

    申请日：2005-12-09

    申请人： Yoshiyuki Ishigaki

    发明人： Yoshiyuki Ishigaki

    IPC分类号： H01L21/8234 ,  H01L29/76

    CPC分类号： H01L21/823842 ,  H01L27/105 ,  H01L27/11293 ,  H01L27/11526 ,  H01L27/11546

    摘要： To improve reliability of FETs having element isolation regions for electrically isolating field effect transistors adjacent to each other in the gate length direction in a mask ROM region, the isolation regions are each constructed by field plate isolation formed simultaneously with gate electrodes of the field effect transistors. This relatively lessens a stress generated in an active region ACT sandwiched by the element isolation regions even if the isolation width of each element isolation region is made relatively small, specifically, less than 0.3 μm. It is therefore possible to relax or prevent the generation of crystal defects resulting from the stress, thereby reducing occurrence of an undesired leak current between the source and drain of each field effect transistor.

    摘要翻译： 为了提高具有元件隔离区域的FET的可靠性，用于隔离掩模ROM区域中的栅极长度方向上彼此相邻的场效应晶体管，隔离区域各自由与场效应晶体管的栅电极同时形成的场板隔离构成 。 即使各元件隔离区域的隔离宽度相对较小，具体而言小于0.3μm，也能够相对地减轻夹在元件隔离区域的有源区域ACT中产生的应力。 因此，可以放松或防止由应力引起的晶体缺陷的产生，从而减少每个场效应晶体管的源极和漏极之间的不期望的漏电流的发生。