公开(公告)号：US07675791B2

公开(公告)日：2010-03-09

申请号：US12480186

申请日：2009-06-08

Applicant: Youn-cheul Kim

Inventor： Youn-cheul Kim

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G11C7/222 ,  G11C7/227

Abstract: A synchronous memory device, which includes a read command buffer, a replica circuit, and a latency circuit. The read command buffer provides a read signal in response to a read command. The replica circuit provides a transfer signal whose time difference with respect to the feedback clock signal is substantially identical to a period that it takes a read command buffer to provide the read signal. The latency circuit receives the read signal, and provides a latency signal having a difference of a predetermined time corresponding to CAS latency with respect to the read signal in response to the transfer signal.

Abstract translation: 同步存储器件，其包括读命令缓冲器，复制电路和延迟电路。 读取命令缓冲器响应读取命令提供读取信号。 复制电路提供传输信号，其相对于反馈时钟信号的时间差基本上与读取命令缓冲器提供读取信号所需的时间相同。 等待时间电路接收读取信号，并响应于传送信号提供相对于读取信号的对应于CAS等待时间的预定时间的差异的等待时间信号。

公开(公告)号：US20070047340A1

公开(公告)日：2007-03-01

申请号：US11511678

申请日：2006-08-29

Applicant: Youn-cheul Kim

Inventor： Youn-cheul Kim

IPC: G11C7/00

CPC classification number: G11C7/1072 ,  G11C7/222 ,  G11C7/227

Abstract: A synchronous memory device, which includes a read command buffer, a replica circuit, and a latency circuit. The read command buffer provides a read signal in response to a read command. The replica circuit provides a transfer signal whose time difference with respect to the feedback clock signal is substantially identical to a period that it takes a read command buffer to provide the read signal. The latency circuit receives the read signal, and provides a latency signal having a difference of a predetermined time corresponding to CAS latency with respect to the read signal in response to the transfer signal.

Abstract translation: 同步存储器件，其包括读命令缓冲器，复制电路和延迟电路。 读取命令缓冲器响应读取命令提供读取信号。 复制电路提供传输信号，其相对于反馈时钟信号的时间差基本上与读取命令缓冲器提供读取信号所需的时间相同。 等待时间电路接收读取信号，并响应于传送信号提供相对于读取信号的对应于CAS等待时间的预定时间的差异的等待时间信号。

公开(公告)号：US07116149B2

公开(公告)日：2006-10-03

申请号：US10804936

申请日：2004-03-19

Applicant: Youn-cheul Kim

Inventor： Youn-cheul Kim

IPC: H03K3/017

CPC classification number: H03K5/1565 ,  H03L7/0812

Abstract: There is provided a Delay Locked Loop (DLL) including a duty cycle correction circuit capable of controlling a duty error, when the duty error is generated in the DLL. The duty cycle correction circuit controls amounts of electric charges accumulated in storage units, in response to switching control signals received from the external, and outputs duty rate control signals each corresponding to a difference between the amounts of electric charges accumulated in the storage units. Therefore, the DLL including the duty cycle correction circuit can correct a duty cycle of a reference clock signal, in response to the duty rate control signals, and can output a reference clock signal with a duty cycle of 50%.

Abstract translation: 提供了当在DLL中产生占空比错误时，包括能够控制占空误差的占空比校正电路的延迟锁定环（DLL）。 占空比校正电路响应于从外部接收的切换控制信号，控制存储单元中积累的电荷量，并且输出各自对应于存储单元中积累的电荷量之差的占空比控制信号。 因此，包括占空比校正电路的DLL可以根据占空比控制信号来校正参考时钟信号的占空比，并可以以50％的占空比输出参考时钟信号。

公开(公告)号：US20090244998A1

公开(公告)日：2009-10-01

申请号：US12480186

申请日：2009-06-08

Applicant: Youn-cheul Kim

Inventor： Youn-cheul Kim

IPC: G11C7/00 ,  G11C8/18

CPC classification number: G11C7/1072 ,  G11C7/222 ,  G11C7/227

Abstract: A synchronous memory device, which includes a read command buffer, a replica circuit, and a latency circuit. The read command buffer provides a read signal in response to a read command. The replica circuit provides a transfer signal whose time difference with respect to the feedback clock signal is substantially identical to a period that it takes a read command buffer to provide the read signal. The latency circuit receives the read signal, and provides a latency signal having a difference of a predetermined time corresponding to CAS latency with respect to the read signal in response to the transfer signal.

Abstract translation: 同步存储器件，其包括读命令缓冲器，复制电路和延迟电路。 读取命令缓冲器响应读取命令提供读取信号。 复制电路提供传输信号，其相对于反馈时钟信号的时间差基本上与读取命令缓冲器提供读取信号所需的时间相同。 等待时间电路接收读取信号，并响应于传送信号提供相对于读取信号的对应于CAS等待时间的预定时间的差异的等待时间信号。

公开(公告)号：US07554878B2

公开(公告)日：2009-06-30

申请号：US11511678

申请日：2006-08-29

Applicant: Youn-cheul Kim

Inventor： Youn-cheul Kim

IPC: G11C8/02

CPC classification number: G11C7/1072 ,  G11C7/222 ,  G11C7/227

Abstract: A synchronous memory device, which includes a read command buffer, a replica circuit, and a latency circuit. The read command buffer provides a read signal in response to a read command. The replica circuit provides a transfer signal whose time difference with respect to the feedback clock signal is substantially identical to a period that it takes a read command buffer to provide the read signal. The latency circuit receives the read signal, and provides a latency signal having a difference of a predetermined time corresponding to CAS latency with respect to the read signal in response to the transfer signal.

Abstract translation: 同步存储器件，其包括读命令缓冲器，复制电路和延迟电路。 读取命令缓冲器响应读取命令提供读取信号。 复制电路提供传输信号，其相对于反馈时钟信号的时间差基本上与读取命令缓冲器提供读取信号所需的时间相同。 等待时间电路接收读取信号，并响应于传送信号提供相对于读取信号的对应于CAS等待时间的预定时间的差异的等待时间信号。

公开(公告)号：US07106612B2

公开(公告)日：2006-09-12

申请号：US11043935

申请日：2005-01-28

Applicant: Youn-cheul Kim

Inventor： Youn-cheul Kim

IPC: G11C5/06

CPC classification number: G11C5/025 ,  G11C11/4097

Abstract: A semiconductor memory device optimizes current consumption by using proper sub-bank arrangement and at least two different kinds of LIO sense amplifiers having different driving capabilities. The driving capabilities of the LIO sense amplifiers are controlled in a tapered manner depending on whether a corresponding sub-bank of the LIO sense amplifier is arranged nearer to, or farther away from, its corresponding GIO sense amplifier. In other words, the farther that a sub-bank of an LIO sense amplifier is away from its corresponding GIO sense amplifier, the greater its driving capability.

Abstract translation: 半导体存储器件通过使用适当的子库布置来优化电流消耗，以及具有不同驱动能力的至少两种不同种类的LIO读出放大器。 LIO读出放大器的驱动能力以锥形方式进行控制，这取决于LIO读出放大器的相应子库是否被布置为更靠近或远离其相应的GIO读出放大器。 换句话说，LIO读出放大器的一个子组离其相应的GIO读出放大器越远，其驱动能力就越大。

公开(公告)号：US07202720B2

公开(公告)日：2007-04-10

申请号：US11130062

申请日：2005-05-16

Applicant: Youn-cheul Kim

Inventor： Youn-cheul Kim

IPC: H03L7/06

CPC classification number: H03K5/1565 ,  H03L7/0812

Abstract: There is provided a Delay Locked Loop (DLL) including a duty cycle correction circuit capable of controlling a duty error, when the duty error is generated in the DLL. The duty cycle correction circuit controls amounts of electric charges accumulated in storage units, in response to switching control signals received from the external, and outputs duty rate control signals each corresponding to a difference between the amounts of electric charges accumulated in the storage units. Therefore, the DLL including the duty cycle correction circuit can correct a duty cycle of a reference clock signal, in response to the duty rate control signals, and can output a reference clock signal with a duty cycle of 50%.

Abstract translation: 提供了当在DLL中产生占空比错误时，包括能够控制占空误差的占空比校正电路的延迟锁定环（DLL）。 占空比校正电路响应于从外部接收的切换控制信号，控制存储单元中积累的电荷量，并且输出各自对应于存储单元中积累的电荷量之差的占空比控制信号。 因此，包括占空比校正电路的DLL可以根据占空比控制信号来校正参考时钟信号的占空比，并可以以50％的占空比输出参考时钟信号。

公开(公告)号：US20050212575A1

公开(公告)日：2005-09-29

申请号：US11130062

申请日：2005-05-16

Applicant: Youn-cheul Kim

Inventor： Youn-cheul Kim

IPC: H03L7/00 ,  H03K5/156 ,  H03L7/081 ,  H03L7/06

CPC classification number: H03K5/1565 ,  H03L7/0812

Abstract: There is provided a Delay Locked Loop (DLL) including a duty cycle correction circuit capable of controlling a duty error, when the duty error is generated in the DLL. The duty cycle correction circuit controls amounts of electric charges accumulated in storage units, in response to switching control signals received from the external, and outputs duty rate control signals each corresponding to a difference between the amounts of electric charges accumulated in the storage units. Therefore, the DLL including the duty cycle correction circuit can correct a duty cycle of a reference clock signal, in response to the duty rate control signals, and can output a reference clock signal with a duty cycle of 50%.

Abstract translation: 提供了当在DLL中产生占空比错误时，包括能够控制占空误差的占空比校正电路的延迟锁定环（DLL）。 占空比校正电路响应于从外部接收的切换控制信号，控制存储单元中积累的电荷量，并且输出各自对应于存储单元中积累的电荷量之差的占空比控制信号。 因此，包括占空比校正电路的DLL可以根据占空比控制信号来校正参考时钟信号的占空比，并可以以50％的占空比输出参考时钟信号。

公开(公告)号：US20050169079A1

公开(公告)日：2005-08-04

申请号：US11043935

申请日：2005-01-28

Applicant: Youn-cheul Kim

Inventor： Youn-cheul Kim

IPC: G11C7/06 ,  G11C5/02 ,  G11C7/02 ,  G11C11/4097

CPC classification number: G11C5/025 ,  G11C11/4097

Abstract: A semiconductor memory device optimizes current consumption by using proper sub-bank arrangement and at least two different kinds of LIO sense amplifiers having different driving capabilities. The driving capabilities of the LIO sense amplifiers are controlled in a tapered manner depending on whether a corresponding sub-bank of the LIO sense amplifier is arranged nearer to, or farther away from, its corresponding GIO sense amplifier. In other words, the farther that a sub-bank of an LIO sense amplifier is away from its corresponding GIO sense amplifier, the greater its driving capability.

Abstract translation: 半导体存储器件通过使用适当的子库布置来优化电流消耗，以及具有不同驱动能力的至少两种不同种类的LIO读出放大器。 LIO读出放大器的驱动能力以锥形方式进行控制，这取决于LIO读出放大器的相应子库是否被布置为更靠近或远离其相应的GIO读出放大器。 换句话说，LIO读出放大器的一个子组离其相应的GIO读出放大器越远，其驱动能力就越大。

公开(公告)号：US06707321B2

公开(公告)日：2004-03-16

申请号：US10401580

申请日：2003-03-31

Applicant: Young-chan Cho ,  Youn-cheul Kim

Inventor： Young-chan Cho ,  Youn-cheul Kim

IPC: G01R1900

CPC classification number: G11C7/106 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1051 ,  G11C7/1069 ,  H03K3/012 ,  H03K3/356139

Abstract: An input receiver controls an offset voltage by using an output feedback signal to improve a sense speed. The input receiver includes a pre-amplifier that controls an offset voltage in response to a feedback signal and amplifies an input signal with reference to a reference voltage. A sense amplifier amplifies an output signal and an inverted output signal of the pre-amplifier in response to a clock signal. A latch circuit latches an output signal and an inverted output signal of the sense amplifier. An inversion circuit uses the reference voltage as a power supply voltage and inverts an inverted output signal of the latch circuit. In addition, an output signal of the inversion circuit is supplied as the feedback signal. Alternatively, the output signal of the latch circuit may be directly supplied to the pre-amplifier as the feedback signal while not using the inversion circuit.

Abstract translation: 输入接收器通过使用输出反馈信号来控制偏移电压以提高感测速度。 输入接收机包括预放大器，其响应于反馈信号控制偏移电压并且参考参考电压放大输入信号。 读出放大器响应于时钟信号放大前置放大器的输出信号和反相输出信号。 锁存电路锁存读出放大器的输出信号和反相输出信号。 反相电路使用参考电压作为电源电压，并且反相锁存电路的反相输出信号。 此外，反相电路的输出信号作为反馈信号被提供。 或者，可以在不使用反相电路的同时将锁存电路的输出信号直接提供给前置放大器作为反馈信号。