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    PREDISTORTER FOR COMPENSATING FOR NONLINEAR DISTORTION AND METHOD THEREOF
    1.
    发明申请
    PREDISTORTER FOR COMPENSATING FOR NONLINEAR DISTORTION AND METHOD THEREOF 有权
    用于补偿非线性失真的预测器及其方法

    公开(公告)号：US20120154040A1

    公开(公告)日：2012-06-21

    申请号：US13330986

    申请日：2011-12-20

    申请人： Young Hoon KIM ,  Gweon Do JO ,  Kwang Chun LEE

    发明人： Young Hoon KIM ,  Gweon Do JO ,  Kwang Chun LEE

    IPC分类号： H03F1/26

    CPC分类号： H03F1/3247 ,  H03F1/3258 ,  H03F3/189 ,  H03F3/24 ,  H03F2201/3212

    摘要： The predistorter may include: a predistortion filter predistorting an input signal to provide an output signal; a predistortion output estimation unit estimating the characteristics of a nonlinear device based on a signal processed by the nonlinear device and the output signal, and calculating a desired output signal of the predistortion filter by using the estimated characteristics of the nonlinear device; and an adaptive algorithm driving unit comparing the output signal with the desired output signal to output an error as a comparison result, calculating a filter coefficient according to which the calculated error is minimized, and providing the calculated filter coefficient to the predistortion filter in order to update a filter coefficient of the predistortion filter.

    摘要翻译： 预失真器可以包括：预失真滤波器预失真输入信号以提供输出信号; 预失真输出估计单元，基于由所述非线性装置处理的信号和所述输出信号来估计所述非线性装置的特性，以及通过使用所述非线性装置的估计特性来计算所述预失真滤波器的期望输出信号; 以及自适应算法驱动单元，将输出信号与期望的输出信号进行比较以输出误差作为比较结果，计算滤波器系数，根据该滤波器系数计算误差最小化，并将计算的滤波器系数提供给预失真滤波器，以便 更新预失真滤波器的滤波器系数。

    METHOD FOR GENERATING DOWNLINK FRAME, AND METHOD FOR SEARCHING CELL
    3.
    发明申请
    METHOD FOR GENERATING DOWNLINK FRAME, AND METHOD FOR SEARCHING CELL 有权
    用于生成下行链路帧的方法，以及用于搜索小区的方法

    公开(公告)号：US20090252335A1

    公开(公告)日：2009-10-08

    申请号：US12488272

    申请日：2009-06-19

    申请人： Kap Seok CHANG ,  Il Gyu KIM ,  Hyeong Geun PARK ,  Young Jo KO ,  Hyo Seok YI ,  Chan Bok JEONG ,  Young Hoon KIM ,  Seung Chan BANG

    发明人： Kap Seok CHANG ,  Il Gyu KIM ,  Hyeong Geun PARK ,  Young Jo KO ,  Hyo Seok YI ,  Chan Bok JEONG ,  Young Hoon KIM ,  Seung Chan BANG

    IPC分类号： H04K1/04

    CPC分类号： H04W48/16 ,  H04B1/70735 ,  H04B7/2656 ,  H04J11/0069 ,  H04L7/043 ,  H04L27/2613 ,  H04L27/2655 ,  H04W56/00 ,  H04W72/042 ,  H04W72/0446 ,  H04W88/08

    摘要： The present invention relates to a method of generating a downlink frame. The method of generating the downlink frame includes: generating a first short sequence and a second short sequence indicating cell group information; generating a first scrambling sequence and a second scrambling sequence determined by the primary synchronization signal; generating a third scrambling sequence determined by the first short sequence and a fourth scrambling sequence determined by the second short sequence; scrambling the first short sequence with the first scrambling sequence and scrambling the second short sequence with the second scrambling sequence and the third scrambling sequence; scrambling the second short sequence with the first scrambling sequence and scrambling the first short sequence with the second scrambling sequence and the fourth scrambling sequence; and mapping the secondary synchronization signal that includes the first short sequence scrambled with the first scrambling sequence, the second short sequence scrambled with the second scrambling sequence and the third scrambling sequence, the second short sequence scrambled with the first scrambling sequence and the first short sequence scrambled by the second scrambling sequence and the fourth scrambling sequence to a frequency domain.

    摘要翻译： 本发明涉及一种生成下行链路帧的方法。 产生下行链路帧的方法包括：产生指示小区组信息的第一短序列和第二短序列; 产生由所述主同步信号确定的第一加扰序列和第二加扰序列; 产生由第一短序列确定的第三加扰序列和由第二短序列确定的第四加扰序列; 用第一加扰序列对第一短序列进行加扰，并用第二加扰序列和第三加扰序列加扰第二短序列; 用第一加扰序列对第二短序列进行加扰，并用第二加扰序列和第四加扰序列对第一短序列进行加扰; 以及映射包括与第一加扰序列加扰的第一短序列的第二同步信号，用第二加扰序列和第三加扰序列加扰的第二短序列，用第一加扰序列和第一短序列加扰的第二短序列 通过第二加扰序列和第四加扰序列加扰到频域。

    METHOD FOR GENERATING DOWNLINK FRAME, AND METHOD FOR SEARCHING CELL
    5.
    发明申请
    METHOD FOR GENERATING DOWNLINK FRAME, AND METHOD FOR SEARCHING CELL 有权
    用于生成下行链路帧的方法，以及用于搜索小区的方法

    公开(公告)号：US20090252333A1

    公开(公告)日：2009-10-08

    申请号：US12488234

    申请日：2009-06-19

    申请人： Kap Seok CHANG ,  Il Gyu KIM ,  Hyeong Geun PARK ,  Young Jo KO ,  Hyo Seok YI ,  Moon Sik LEE ,  Young Hoon KIM ,  Seung Chan BANG

    发明人： Kap Seok CHANG ,  Il Gyu KIM ,  Hyeong Geun PARK ,  Young Jo KO ,  Hyo Seok YI ,  Moon Sik LEE ,  Young Hoon KIM ,  Seung Chan BANG

    IPC分类号： H04K1/04

    CPC分类号： H04W56/00 ,  H04J11/0069 ,  H04J11/0076 ,  H04L25/03866 ,  H04L27/2613 ,  H04L27/2655 ,  H04L27/2656 ,  H04L27/2657 ,  H04L27/2662

    摘要： The present invention relates to a method for generating a downlink frame includes: generating a first short sequence and a second short sequence indicating cell group information; generating a first scrambling sequence determined by a first synchronization signal; generating a second scrambling sequence determined by a group to which the first short sequence belongs, the wireless communication system using a plurality of short sequences and the plurality of short sequence being divided into a plurality of groups; scrambling the first short sequence with the first scrambling sequence; scrambling the second short sequence with at least the second scrambling sequence; and mapping a second synchronization signal including the scrambled first short sequence and the scrambled second short sequence in the frequency domain.

    摘要翻译： 本发明涉及生成下行链路帧的方法，包括：产生指示小区组信息的第一短序列和第二短序列; 产生由第一同步信号确定的第一加扰序列; 生成由第一短序列所属的组确定的第二加扰序列，使用多个短序列的无线通信系统，并且将多个短序列分成多个组; 用第一加扰序列加扰第一短序列; 用至少第二加扰序列来加扰第二短序列; 以及在频域中映射包括加扰的第一短序列和加扰的第二短序列的第二同步信号。

    DUAL GATE OF SEMICONDUCTOR DEVICE CAPABLE OF FORMING A LAYER DOPED IN HIGH CONCENTRATION OVER A RECESSED PORTION OF SUBSTRATE FOR FORMING DUAL GATE WITH RECESS CHANNEL STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    7.
    发明申请
    DUAL GATE OF SEMICONDUCTOR DEVICE CAPABLE OF FORMING A LAYER DOPED IN HIGH CONCENTRATION OVER A RECESSED PORTION OF SUBSTRATE FOR FORMING DUAL GATE WITH RECESS CHANNEL STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 失效
    形成用于形成用于形成具有输入通道结构的双门基板的基板的高浓度层的半导体器件的双栅极及其制造方法

    公开(公告)号：US20090121224A1

    公开(公告)日：2009-05-14

    申请号：US11968461

    申请日：2008-01-02

    申请人： Young Hoon KIM

    发明人： Young Hoon KIM

    IPC分类号： H01L29/78 ,  H01L21/28

    CPC分类号： H01L29/1037 ,  H01L21/2807 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/4966 ,  H01L29/66621

    摘要： A dual gate of a semiconductor device includes a semiconductor substrate divided into a cell region with a recessed gate forming area and a peripheral region with PMOS and NMOS forming areas; first and second conductive type SiGe layers, the first conductive type SiGe layer being formed over the cell region and the PMOS forming area of the peripheral region, and the second conductive type SiGe layer being formed over the NMOS forming area of the peripheral region; first and second conductive type polysilicon layers, the first conductive type polysilicon layer being formed over the first conductive type SiGe layer and the second conductive type polysilicon layer being formed over the second conductive type SiGe layer; and a metallic layer and a hard mask layer stacked over the first and second conductive type polysilicon layers.

    摘要翻译： 半导体器件的双栅极包括分为具有凹入栅极形成区域的单元区域和具有PMOS和NMOS形成区域的外围区域的半导体衬底; 第一导电型SiGe层和第二导电型SiGe层，第一导电型SiGe层形成在晶胞区域和外围区域的PMOS形成区域上，第二导电型SiGe层形成在周边区域的NMOS形成区域上; 第一导电型多晶硅层和第二导电型多晶硅层，第一导电型多晶硅层形成在第一导电型SiGe层上，第二导电型多晶硅层形成在第二导电型SiGe层上; 以及堆叠在第一和第二导电型多晶硅层上的金属层和硬掩模层。

    DUAL GATE OF SEMICONDUCTOR DEVICE CAPABLE OF FORMING A LAYER DOPED IN HIGH CONCENTRATION OVER A RECESSED PORTION OF SUBSTRATE FOR FORMING DUAL GATE WITH RECESS CHANNEL STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    9.
    发明申请
    DUAL GATE OF SEMICONDUCTOR DEVICE CAPABLE OF FORMING A LAYER DOPED IN HIGH CONCENTRATION OVER A RECESSED PORTION OF SUBSTRATE FOR FORMING DUAL GATE WITH RECESS CHANNEL STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 失效
    形成用于形成用于形成具有输入通道结构的双门基板的基板的高浓度层的半导体器件的双栅极及其制造方法

    公开(公告)号：US20100289077A1

    公开(公告)日：2010-11-18

    申请号：US12843184

    申请日：2010-07-26

    申请人： Young Hoon KIM

    发明人： Young Hoon KIM

    IPC分类号： H01L27/092

    CPC分类号： H01L29/1037 ,  H01L21/2807 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/4966 ,  H01L29/66621

    摘要： A dual gate of a semiconductor device includes a semiconductor substrate divided into a cell region with a recessed gate forming area and a peripheral region with PMOS and NMOS forming areas; first and second conductive type SiGe layers, the first conductive type SiGe layer being formed over the cell region and the PMOS forming area of the peripheral region, and the second conductive type SiGe layer being formed over the NMOS forming area of the peripheral region; first and second conductive type polysilicon layers, the first conductive type polysilicon layer being formed over the first conductive type SiGe layer and the second conductive type polysilicon layer being formed over the second conductive type SiGe layer; and a metallic layer and a hard mask layer stacked over the first and second conductive type polysilicon layers.

    摘要翻译： 半导体器件的双栅极包括分为具有凹入栅极形成区域的单元区域和具有PMOS和NMOS形成区域的外围区域的半导体衬底; 第一导电型SiGe层和第二导电型SiGe层，第一导电型SiGe层形成在晶胞区域和外围区域的PMOS形成区域上，第二导电型SiGe层形成在周边区域的NMOS形成区域上; 第一导电型多晶硅层和第二导电型多晶硅层，第一导电型多晶硅层形成在第一导电型SiGe层上，第二导电型多晶硅层形成在第二导电型SiGe层上; 以及堆叠在第一和第二导电型多晶硅层上的金属层和硬掩模层。

    METHOD FOR GENERATING DOWNLINK FRAME, AND METHOD FOR SEARCHING CELL
    10.
    发明申请
    METHOD FOR GENERATING DOWNLINK FRAME, AND METHOD FOR SEARCHING CELL 有权
    用于生成下行链路帧的方法，以及用于搜索小区的方法

    公开(公告)号：US20090252336A1

    公开(公告)日：2009-10-08

    申请号：US12488286

    申请日：2009-06-19

    申请人： Kap Seok CHANG ,  Il Gyu KIM ,  Hyeong Geun PARK ,  Young Jo KO ,  Hyo Seok YI ,  Chan Bok JEONG ,  Young Hoon KIM ,  Seung Chan BANG

    发明人： Kap Seok CHANG ,  Il Gyu KIM ,  Hyeong Geun PARK ,  Young Jo KO ,  Hyo Seok YI ,  Chan Bok JEONG ,  Young Hoon KIM ,  Seung Chan BANG

    IPC分类号： H04K1/04

    CPC分类号： H04W48/16 ,  H04B1/70735 ,  H04B7/2656 ,  H04J11/0069 ,  H04L7/043 ,  H04L27/2613 ,  H04L27/2655 ,  H04W56/00 ,  H04W72/042 ,  H04W72/0446 ,  H04W88/08

    摘要： The present invention relates to a method of generating a downlink frame. The method of generating the downlink frame includes: generating a first short sequence and a second short sequence indicating cell group information; generating a first scrambling sequence and a second scrambling sequence determined by the primary synchronization signal; generating a third scrambling sequence determined by a short sequence group-a wireless communication system uses a plurality of short sequences and the plurality of short sequences are grouped into a plurality of short sequence group-to which the first short sequence is assigned; scrambling the first short sequence with the first scrambling sequence and scrambling the second short sequence with the second scrambling sequence and the third scrambling sequence; and mapping the secondary synchronization signal that includes the scrambled first short sequence and the scrambled second short sequence to a frequency domain.

    摘要翻译： 本发明涉及一种生成下行链路帧的方法。 产生下行链路帧的方法包括：产生指示小区组信息的第一短序列和第二短序列; 产生由所述主同步信号确定的第一加扰序列和第二加扰序列; 产生由短序列组确定的第三加扰序列 - 无线通信系统使用多个短序列，并且将多个短序列分组成分配有第一短序列的多个短序列组; 用第一加扰序列对第一短序列进行加扰，并用第二加扰序列和第三加扰序列加扰第二短序列; 以及将包括加扰的第一短序列和加扰的第二短序列的次同步信号映射到频域。