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    Method for fabricating a semiconductor device including the use of a compound containing silicon and nitrogen to form an insulation film of SiN, SiCN or SiOCN
    1.
    发明申请
    Method for fabricating a semiconductor device including the use of a compound containing silicon and nitrogen to form an insulation film of SiN, SiCN or SiOCN 审中-公开
    包括使用含有硅和氮的化合物形成SiN，SiCN或SiOCN的绝缘膜的半导体器件的制造方法

    公开(公告)号：US20070072381A1

    公开(公告)日：2007-03-29

    申请号：US11606271

    申请日：2006-11-30

    申请人： Masayuki Furuhashi ,  Toshifumi Mori ,  Young Kim ,  Takayuki Ohba ,  Ryou Nakamura

    发明人： Masayuki Furuhashi ,  Toshifumi Mori ,  Young Kim ,  Takayuki Ohba ,  Ryou Nakamura

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823814 ,  H01L21/823842

    摘要： The semiconductor device fabrication method comprises the step of forming gate electrode 20 on a semiconductor substrate 10 with a gate insulation film 18 formed therebetween; the step of implanting dopants in the semiconductor substrate 10 with the gate electrode 20 as the mask to form dopant diffused regions 28, 36; the step of forming a silicon oxide film 38 on the semiconductor substrate 10, covering the gate electrodes 20; anisotropically etching the silicon oxide film 38 to form sidewall spacers 42 including the silicon oxide film 38 on the side walls of the gate electrode 20. In the step of forming a silicon oxide film 38, the silicon oxide film 38 is formed by thermal CVD at a 500-580° C. film forming temperature, using bis (tertiary-butylamino) silane and oxygen as raw materials. Silicon oxide film 38 is formed at a relatively low film forming temperature, whereby the diffusion of the dopant in the dopant diffused regions 28, 36 forming the shallow region of the extension source/drain structure can be suppressed.

    摘要翻译： 半导体器件制造方法包括在半导体衬底10上形成栅电极20的步骤，其间形成有栅极绝缘膜18; 以栅电极20为掩模，在半导体衬底10中注入掺杂剂以形成掺杂剂扩散区域28,36的步骤; 在半导体衬底10上形成覆盖栅电极20的氧化硅膜38的步骤; 各向异性地蚀刻氧化硅膜38以在栅电极20的侧壁上形成包括氧化硅膜38的侧壁间隔物42。 在形成氧化硅膜38的步骤中，使用双（叔丁基氨基）硅烷和氧气作为原料，通过热CVD在500-580℃成膜温度下形成氧化硅膜38。 在相对低的成膜温度下形成氧化硅膜38，由此能够抑制形成扩展源极/漏极结构的浅区域的掺杂剂扩散区域28,36中的掺杂剂的扩散。

    Semiconductor device fabricating method
    2.
    发明申请
    Semiconductor device fabricating method 有权
    半导体器件制造方法

    公开(公告)号：US20050266631A1

    公开(公告)日：2005-12-01

    申请号：US11098567

    申请日：2005-04-05

    申请人： Young Kim ,  Toshifumi Mori

    发明人： Young Kim ,  Toshifumi Mori

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

    摘要： Compression stress applying portions 20 of SiGe film are formed in the source/drain regions of the p-MOSA region 30a. Then, impurities are implanted in the p-MOS region 30a and the n-MOS region 30b to form shallow junction regions 22a, 22b and deep junction regions 23a, 23b. The impurity in the shallow junction regions 22a, 22b is prevented from being diffused immediately below the gate insulation film 15 by the thermal processing in forming the SiGe film, the short channel effect is prevented, and the hole mobility of the channel region of the p-MOS transistor 14a. The operation speed of the p-MOS transistor 13a is balanced with that of the n-MOS transistor, whereby the operation speed of the complementary semiconductor device 10 can be increased. The semiconductor device fabricating method can increase and balance the operation speed of a p-transistor with that of an n-transistor.

    摘要翻译： 在p-MOSA区域30a的源极/漏极区域中形成SiGe膜的压应力施加部分20。 然后，在p-MOS区域30a和n-MOS区域30b中注入杂质以形成浅结区域22a，22b和深结区域23a，23b。 通过在形成SiGe膜中的热处理，防止浅结区域22a，22b中的杂质在栅极绝缘膜15的正下方扩散，防止短沟道效应，并且沟道区域的空穴迁移率 p-MOS晶体管14a。 p-MOS晶体管13a的工作速度与n-MOS晶体管的操作速度平衡，可以提高互补半导体器件10的工作速度。 半导体器件制造方法可以增加并平衡p型晶体管与n型晶体管的工作速度。

    Method of fabricating a complementary semiconductor device having a strained channel p-transistor
    3.
    发明授权
    Method of fabricating a complementary semiconductor device having a strained channel p-transistor 有权
    制造具有应变通道p型晶体管的互补半导体器件的方法

    公开(公告)号：US07407860B2

    公开(公告)日：2008-08-05

    申请号：US11098567

    申请日：2005-04-05

    申请人： Young Suk Kim ,  Toshifumi Mori

    发明人： Young Suk Kim ,  Toshifumi Mori

    IPC分类号： H01L21/336 ,  H01L21/76

    CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

    摘要： Compression stress applying portions 20 of SiGe film are formed in the source/drain regions of the p-MOSA region 30a. Then, impurities are implanted in the p-MOS region 30a and the n-MOS region 30b to form shallow junction regions 22a, 22b and deep junction regions 23a, 23b. The impurity in the shallow junction regions 22a, 22b is prevented from being diffused immediately below the gate insulation film 15 by the thermal processing in forming the SiGe film, the short channel effect is prevented, and the hole mobility of the channel region of the p-MOS transistor 14a. The operation speed of the p-MOS transistor 13a is balanced with that of the n-MOS transistor, whereby the operation speed of the complementary semiconductor device 10 can be increased. The semiconductor device fabricating method can increase and balance the operation speed of a p-transistor with that of an n-transistor.

    摘要翻译： 在p-MOSA区域30a的源极/漏极区域中形成SiGe膜的压应力施加部分20。 然后，在p-MOS区域30a和n-MOS区域30b中注入杂质以形成浅结区域22a，22b和深结区域23a，23b。 通过在形成SiGe膜中的热处理，防止浅结区域22a，22b中的杂质在栅极绝缘膜15的正下方扩散，防止短沟道效应，并且沟道区域的空穴迁移率 p-MOS晶体管14a。 p-MOS晶体管13a的工作速度与n-MOS晶体管的操作速度平衡，可以提高互补半导体器件10的工作速度。 半导体器件制造方法可以增加并平衡p型晶体管与n型晶体管的工作速度。

    Method for fabricating a semiconductor device including the use of a compound containing silicon and nitrogen to form an insulation film of SiN or SiCN
    4.
    发明授权
    Method for fabricating a semiconductor device including the use of a compound containing silicon and nitrogen to form an insulation film of SiN or SiCN 有权
    一种制造半导体器件的方法，包括使用含有硅和氮的化合物以形成SiN或SiCN的绝缘膜

    公开(公告)号：US07166516B2

    公开(公告)日：2007-01-23

    申请号：US10696775

    申请日：2003-10-30

    申请人： Masayuki Furuhashi ,  Toshifumi Mori ,  Young Suk Kim ,  Takayuki Ohba ,  Ryou Nakamura

    发明人： Masayuki Furuhashi ,  Toshifumi Mori ,  Young Suk Kim ,  Takayuki Ohba ,  Ryou Nakamura

    IPC分类号： H01L21/471 ,  C23C16/34 ,  C23C16/36

    CPC分类号： H01L21/823814 ,  H01L21/823842

    摘要： The semiconductor device fabrication method comprises the step of forming gate electrode 20 on a semiconductor substrate 10 with a gate insulation film 18 formed therebetween; the step of implanting dopants in the semiconductor substrate 10 with the gate electrode 20 as the mask to form dopant diffused regions 28, 36; the step of forming a silicon oxide film 38 on the semiconductor substrate 10, covering the gate electrodes 20; anisotropically etching the silicon oxide film 38 to form sidewall spacers 42 including the silicon oxide film 38 on the side walls of the gate electrode 20. In the step of forming a silicon oxide film 38, the silicon oxide film 38 is formed by thermal CVD at a 500–580° C. film forming temperature, using bis(tertiary-butylamino)silane and oxygen as raw materials. Silicon oxide film 38 is formed at a relatively low film forming temperature, whereby the diffusion of the dopant in the doapnt diffused regions 28, 36 forming the shallow region of the extension source/drain structure can be suppressed.

    摘要翻译： 半导体器件制造方法包括在半导体衬底10上形成栅电极20的步骤，其间形成有栅极绝缘膜18; 以栅电极20为掩模，在半导体衬底10中注入掺杂剂以形成掺杂剂扩散区域28,36的步骤; 在半导体衬底10上形成覆盖栅电极20的氧化硅膜38的步骤; 各向异性地蚀刻氧化硅膜38以在栅电极20的侧壁上形成包括氧化硅膜38的侧壁间隔物42。 在形成氧化硅膜38的步骤中，使用双（叔丁基氨基）硅烷和氧气作为原料，通过热CVD在500-580℃成膜温度下形成氧化硅膜38。 在相对较低的成膜温度下形成氧化硅膜38，由此可以抑制形成扩展源极/漏极结构的浅区域的多个扩散区域28,36中的掺杂剂的扩散。

    Open-bottom gravel dump boat
    5.
    发明授权
    Open-bottom gravel dump boat 失效
    开放式砾石倾倒船

    公开(公告)号：US5012754A

    公开(公告)日：1991-05-07

    申请号：US72265

    申请日：1987-09-08

    申请人： Toshifumi Mori

    发明人： Toshifumi Mori

    IPC分类号： B63B35/30

    CPC分类号： B63B35/308

    摘要： A hull construction of a cargo carrier vessel, with self-propelling capacity, capable of carrying earth, sand, quarried stones and so forth and of disposing of them from the bottom is disclosed. While the bottom (11) is released, the hold forms a double-hull construction with side walls (12). A pair of right and left doors, each with an L-shaped section, is provided. The upper part of each door is connected by hinges to outsides of the side walls of said hold. The doors curve and extend along the released bottom. Cargo is carried in the hold (1). Furthermore, a door structure to dispose of cargo from the released bottom into the sea by releasing it to the right and left and equipment to open and close the pair of doors, located at the front and back of the door structure, is provided.

    摘要翻译： PCT No.PCT / JP86 / 00559 Sec。 371日期1987年9月8日 102（e）日期1987年9月8日PCT公布1986年11月5日PCT公布。 公开号WO87 / 02960 日期：1987年5月21日。披露了具有自推进能力，能够运载地球，沙子，采石等等并从底部处置的货船的船体结构。 当底部（11）被释放时，挡板形成具有侧壁（12）的双壳体结构。 提供了一对左右门，每个都有一个L形的部分。 每个门的上部通过铰链连接到所述保持件的侧壁的外侧。 门沿着释放的底部曲线并延伸。 货物在货舱（1）中。 另外，还提供了一种将货物从释放的底部向左右释放并将设备打开和关闭位于门结构的前后的一对门的门结构。

    ORGANIC ELECTROLUMINESCENT DISPLAY APPARATUS
    7.
    发明申请
    ORGANIC ELECTROLUMINESCENT DISPLAY APPARATUS 有权
    有机电致发光显示装置

    公开(公告)号：US20100090592A1

    公开(公告)日：2010-04-15

    申请号：US12573346

    申请日：2009-10-05

    申请人： Satoru Shiobara ,  Toshifumi Mori ,  Kenichi Ikari ,  Koichi Suzuki ,  Akira Tsuboyama

    发明人： Satoru Shiobara ,  Toshifumi Mori ,  Kenichi Ikari ,  Koichi Suzuki ,  Akira Tsuboyama

    IPC分类号： H01J1/62

    CPC分类号： H01L51/5012 ,  H01L27/3211 ,  H01L51/5048 ,  H01L51/5265

    摘要： An organic electroluminescent display apparatus having organic electroluminescent devices each of which is excellent in color reproducibility and has high emission efficiency in which green organic electroluminescent devices each have a delayed fluorescent material and a microcavity, and the hole transport layer of each of the devices has the same thickness as that of the hole transport layer of each of blue organic electroluminescent devices.

    摘要翻译： 一种具有有机电致发光器件的有机电致发光器件，其各自具有优异的色彩再现性，并且具有高发光效率，其中绿色有机电致发光器件各自具有延迟的荧光材料和微腔，并且每个器件的空穴传输层具有 与蓝色有机电致发光器件的每个的空穴传输层的厚度相同。

    Method for minimizing defects in a semiconductor substrate due to ion implantation
    9.
    发明授权
    Method for minimizing defects in a semiconductor substrate due to ion implantation 有权
    由于离子注入使半导体衬底中的缺陷最小化的方法

    公开(公告)号：US08858818B2

    公开(公告)日：2014-10-14

    申请号：US12895730

    申请日：2010-09-30

    申请人： Pushkar Ranade ,  Toshifumi Mori ,  Ken-ichi Okabe ,  Toshiki Miyake

    发明人： Pushkar Ranade ,  Toshifumi Mori ,  Ken-ichi Okabe ,  Toshiki Miyake

    IPC分类号： C23F1/00 ,  C03C15/00 ,  C03C25/68 ,  H01L21/302 ,  H01L21/461 ,  H01L21/265

    CPC分类号： H01L21/26513 ,  H01L21/26506

    摘要： The effects of knock-on oxide in a semiconductor substrate are reduced by providing a semiconductor substrate and forming a thin layer of native oxide on the semiconductor substrate. Ion implantation is performed through the native oxide layer. The native oxide layer reduces the phenomenon of knock-on oxide and oxygen concentration within the semiconductor substrate. Further reduction may be achieved by etching the surface of the semiconductor substrate in order to eliminate a concentration of oxygen at a surface of the semiconductor substrate.

    摘要翻译： 通过提供半导体衬底并在半导体衬底上形成天然氧化物的薄层来减少半导体衬底中的环氧化物的影响。 通过天然氧化物层进行离子注入。 天然氧化物层减少了半导体衬底内的氧化物和氧浓度的现象。 可以通过蚀刻半导体衬底的表面以消除半导体衬底的表面处的氧浓度来实现进一步的还原。