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    Semiconductor device and method for manufacturing the same
    3.
    发明申请
    Semiconductor device and method for manufacturing the same 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20060121714A1

    公开(公告)日：2006-06-08

    申请号：US11103562

    申请日：2005-04-12

    申请人： Hiroyuki Ohta ,  Katsuaki Ookoshi ,  Toshifumi Mori

    发明人： Hiroyuki Ohta ,  Katsuaki Ookoshi ,  Toshifumi Mori

    IPC分类号： H01L21/3205

    CPC分类号： H01L21/02115 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/28518 ,  H01L21/3145 ,  H01L21/76837 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    摘要： Disclosed is a method for manufacturing a semiconductor device provided with a sidewall having a high quality and an excellent shape. The sidewall on a gate electrode side wall is formed using a carbon-containing silicon nitride oxide film. The film can be formed by a CVD method using, as starting materials, BTBAS and oxygen where a BTBAS flow rate/oxygen flow rate ratio is appropriately set and a low film formation temperature is set, for example, at about 530° C. When forming the sidewall using this film, improvement in HF resistance and reduction in fringe capacitance can be realized due to contribution of nitrogen atoms and carbon atoms. Further, when forming this film under low temperature conditions, unnecessary diffusion of impurities introduced into a semiconductor substrate can be suppressed. Thus, transistor characteristics are enhanced and stabilized, so that high performance and high quality in the semiconductor device can be realized.

    摘要翻译： 公开了一种具有高质量和优良形状的侧壁的半导体器件的制造方法。 栅电极侧壁上的侧壁使用含碳氮氧化硅膜形成。 可以通过使用BTBAS和氧气作为原料的BTBAS流量/氧气流量比适当设定并且低成膜温度设定为例如约530℃的CVD法形成。当 使用该膜形成侧壁，由于氮原子和碳原子的贡献，可以实现HF电阻的提高和边缘电容的降低。 此外，当在低温条件下形成该膜时，可以抑制引入到半导体衬底中的杂质的不必要的扩散。 因此，晶体管特性得到增强和稳定，从而可以实现半导体器件的高性能和高质量。

    Semiconductor device having buffer layer between sidewall insulating film and semiconductor substrate
    4.
    发明授权
    Semiconductor device having buffer layer between sidewall insulating film and semiconductor substrate 有权
    在侧壁绝缘膜和半导体衬底之间具有缓冲层的半导体器件

    公开(公告)号：US07906798B2

    公开(公告)日：2011-03-15

    申请号：US11950102

    申请日：2007-12-04

    申请人： Hiroyuki Ohta ,  Katsuaki Ookoshi

    发明人： Hiroyuki Ohta ,  Katsuaki Ookoshi

    IPC分类号： H01L27/092

    CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

    摘要： A semiconductor device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a channel area formed in a silicon substrate, a gate electrode formed on a gate insulating film in correspondence with the channel area, and a source area and a drain area formed in the silicon substrate having the channel area situated therebetween. The PMOS transistor includes another channel area formed in the silicon substrate, another gate electrode formed on another gate insulating film in correspondence with the other channel area, and another source area and another drain area formed in the silicon substrate having the other channel area situated therebetween. The gate electrode has first sidewall insulating films. The other gate electrode has second sidewall insulating films. The distance between the second sidewall insulating films and the silicon substrate is greater than the distance between the first sidewall insulating films and the silicon substrate.

    摘要翻译： 半导体器件包括NMOS晶体管和PMOS晶体管。 NMOS晶体管包括形成在硅衬底中的沟道区，形成在与沟道区相对应的栅极绝缘膜上的栅电极，以及形成在硅衬底中的沟道区的源极区和漏区，位于其间。 PMOS晶体管包括形成在硅衬底中的另一沟道区，与另一沟道区相对应的另一栅极电极上形成的另一栅电极，以及形成在硅衬底中的另一源极区和另一漏极区，其另一沟道区位于其间 。 栅电极具有第一侧壁绝缘膜。 另一个栅电极具有第二侧壁绝缘膜。 第二侧壁绝缘膜和硅衬底之间的距离大于第一侧壁绝缘膜和硅衬底之间的距离。

    Method of forming semiconductor device having buffer layer between sidewall insulating film and semiconductor substrate
    6.
    发明授权
    Method of forming semiconductor device having buffer layer between sidewall insulating film and semiconductor substrate 有权
    在侧壁绝缘膜和半导体衬底之间形成具有缓冲层的半导体器件的方法

    公开(公告)号：US08481383B2

    公开(公告)日：2013-07-09

    申请号：US13024988

    申请日：2011-02-10

    申请人： Hiroyuki Ohta ,  Katsuaki Ookoshi

    发明人： Hiroyuki Ohta ,  Katsuaki Ookoshi

    IPC分类号： H01L21/8238 ,  H01L27/092

    CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

    摘要： A semiconductor device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a channel area formed in a silicon substrate, a gate electrode formed on a gate insulating film in correspondence with the channel area, and a source area and a drain area formed in the silicon substrate having the channel area situated therebetween. The PMOS transistor includes another channel area formed in the silicon substrate, another gate electrode formed on another gate insulating film in correspondence with the other channel area, and another source area and another drain area formed in the silicon substrate having the other channel area situated therebetween. The gate electrode has first sidewall insulating films. The other gate electrode has second sidewall insulating films. The distance between the second sidewall insulating films and the silicon substrate is greater than the distance between the first sidewall insulating films and the silicon substrate.

    摘要翻译： 半导体器件包括NMOS晶体管和PMOS晶体管。 NMOS晶体管包括形成在硅衬底中的沟道区，形成在与沟道区相对应的栅极绝缘膜上的栅电极，以及形成在硅衬底中的沟道区的源极区和漏区，位于其间。 PMOS晶体管包括形成在硅衬底中的另一沟道区，与另一沟道区相对应的另一栅极电极上形成的另一栅电极，以及形成在硅衬底中的另一源极区和另一漏极区，其另一沟道区位于其间 。 栅电极具有第一侧壁绝缘膜。 另一个栅电极具有第二侧壁绝缘膜。 第二侧壁绝缘膜和硅衬底之间的距离大于第一侧壁绝缘膜和硅衬底之间的距离。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
    半导体器件及制造半导体器件的方法

    公开(公告)号：US20080142838A1

    公开(公告)日：2008-06-19

    申请号：US11950102

    申请日：2007-12-04

    申请人： Hiroyuki Ohta ,  Katsuaki Ookoshi

    发明人： Hiroyuki Ohta ,  Katsuaki Ookoshi

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

    摘要： A semiconductor device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a channel area formed in a silicon substrate, a gate electrode formed on a gate insulating film in correspondence with the channel area, and a source area and a drain area formed in the silicon substrate having the channel area situated therebetween. The PMOS transistor includes another channel area formed in the silicon substrate, another gate electrode formed on another gate insulating film in correspondence with the other channel area, and another source area and another drain area formed in the silicon substrate having the other channel area situated therebetween. The gate electrode has first sidewall insulating films. The other gate electrode has second sidewall insulating films. The distance between the second sidewall insulating films and the silicon substrate is greater than the distance between the first sidewall insulating films and the silicon substrate.

    摘要翻译： 半导体器件包括NMOS晶体管和PMOS晶体管。 NMOS晶体管包括形成在硅衬底中的沟道区，形成在与沟道区相对应的栅极绝缘膜上的栅电极，以及形成在硅衬底中的沟道区的源极区和漏区，位于其间。 PMOS晶体管包括形成在硅衬底中的另一沟道区，与另一沟道区相对应的另一栅极电极上形成的另一栅电极，以及形成在硅衬底中的另一源极区和另一漏极区，其另一沟道区位于其间 。 栅电极具有第一侧壁绝缘膜。 另一个栅电极具有第二侧壁绝缘膜。 第二侧壁绝缘膜和硅衬底之间的距离大于第一侧壁绝缘膜和硅衬底之间的距离。

    Method of manufacturing semiconductor device
    9.
    发明授权
    Method of manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07883960B2

    公开(公告)日：2011-02-08

    申请号：US12409979

    申请日：2009-03-24

    申请人： Masatoshi Fukuda ,  Akiyoshi Hatada ,  Katsuaki Ookoshi ,  Kenichi Okabe ,  Tomonari Yamamoto

    发明人： Masatoshi Fukuda ,  Akiyoshi Hatada ,  Katsuaki Ookoshi ,  Kenichi Okabe ,  Tomonari Yamamoto

    IPC分类号： H01L21/8234 ,  H01L21/8244 ,  H01L21/8242 ,  H01L21/336

    CPC分类号： H01L27/0629

    摘要： A method of manufacturing a semiconductor device includes forming a conductive layer over a semiconductor substrate, selectively removing the conductive layer for forming a resistance element and a gate electrode, forming sidewall spacers over sidewalls of the remaining conductive layer, forming a first insulating film containing a nitrogen over the semiconductor substrate having the sidewall spacers, implanting ions in the semiconductor substrate through the first insulating film, forming a second insulating film containing a nitrogen over the first insulating film after implanting ions in the semiconductor substrate through the first insulating film, and selectively removing the first and the second insulating film such that at least a part of the first and the second insulating films is remained over the semiconductor substrate and over the conductive layer.

    摘要翻译： 一种制造半导体器件的方法包括在半导体衬底上形成导电层，选择性地去除用于形成电阻元件和栅电极的导电层，在剩余导电层的侧壁上形成侧壁间隔物，形成第一绝缘膜， 在具有侧壁间隔物的半导体衬底上的氮气，通过第一绝缘膜在半导体衬底中注入离子，在通过第一绝缘膜植入离子到半导体衬底中之后，在第一绝缘膜上形成含有氮的第二绝缘膜，并且选择性地 去除第一和第二绝缘膜，使得第一和第二绝缘膜的至少一部分保留在半导体衬底上并在导电层上方。

    Method of manufacturing semiconductor device
    10.
    发明授权
    Method of manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US08409958B2

    公开(公告)日：2013-04-02

    申请号：US13190696

    申请日：2011-07-26

    申请人： Katsuaki Ookoshi ,  Masatoshi Nishikawa ,  Yosuke Shimamune

    发明人： Katsuaki Ookoshi ,  Masatoshi Nishikawa ,  Yosuke Shimamune

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L29/7848

    摘要： A method of manufacturing a semiconductor device is provided. The method includes forming a gate electrode on a semiconductor substrate; forming a dopant implantation area in the semiconductor substrate by implanting a dopant in the semiconductor substrate, using the gate electrode as a mask; forming sidewalls on the gate electrode; forming a first recess by etching the semiconductor substrate, using the gate electrode and the sidewalls as a mask; forming a second recess by removing the dopant implantation area positioned below the sidewalls; and forming a source area and a drain area by causing a semiconductor material to grow in the first recess and the second recess.

    摘要翻译： 提供一种制造半导体器件的方法。 该方法包括在半导体衬底上形成栅电极; 通过使用栅电极作为掩模在半导体衬底中注入掺杂剂，在半导体衬底中形成掺杂剂注入区; 在所述栅电极上形成侧壁; 通过蚀刻所述半导体衬底，使用所述栅电极和所述侧壁作为掩模来形成第一凹部; 通过去除位于侧壁下方的掺杂剂注入区域形成第二凹槽; 以及通过使半导体材料在所述第一凹部和所述第二凹部中生长而形成源极区域和漏极区域。