公开(公告)号：US20070072381A1

公开(公告)日：2007-03-29

申请号：US11606271

申请日：2006-11-30

申请人： Masayuki Furuhashi ,  Toshifumi Mori ,  Young Kim ,  Takayuki Ohba ,  Ryou Nakamura

发明人： Masayuki Furuhashi ,  Toshifumi Mori ,  Young Kim ,  Takayuki Ohba ,  Ryou Nakamura

IPC分类号： H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/823842

摘要： The semiconductor device fabrication method comprises the step of forming gate electrode 20 on a semiconductor substrate 10 with a gate insulation film 18 formed therebetween; the step of implanting dopants in the semiconductor substrate 10 with the gate electrode 20 as the mask to form dopant diffused regions 28, 36; the step of forming a silicon oxide film 38 on the semiconductor substrate 10, covering the gate electrodes 20; anisotropically etching the silicon oxide film 38 to form sidewall spacers 42 including the silicon oxide film 38 on the side walls of the gate electrode 20. In the step of forming a silicon oxide film 38, the silicon oxide film 38 is formed by thermal CVD at a 500-580° C. film forming temperature, using bis (tertiary-butylamino) silane and oxygen as raw materials. Silicon oxide film 38 is formed at a relatively low film forming temperature, whereby the diffusion of the dopant in the dopant diffused regions 28, 36 forming the shallow region of the extension source/drain structure can be suppressed.

摘要翻译： 半导体器件制造方法包括在半导体衬底10上形成栅电极20的步骤，其间形成有栅极绝缘膜18; 以栅电极20为掩模，在半导体衬底10中注入掺杂剂以形成掺杂剂扩散区域28,36的步骤; 在半导体衬底10上形成覆盖栅电极20的氧化硅膜38的步骤; 各向异性地蚀刻氧化硅膜38以在栅电极20的侧壁上形成包括氧化硅膜38的侧壁间隔物42。 在形成氧化硅膜38的步骤中，使用双（叔丁基氨基）硅烷和氧气作为原料，通过热CVD在500-580℃成膜温度下形成氧化硅膜38。 在相对低的成膜温度下形成氧化硅膜38，由此能够抑制形成扩展源极/漏极结构的浅区域的掺杂剂扩散区域28,36中的掺杂剂的扩散。

公开(公告)号：US07166516B2

公开(公告)日：2007-01-23

申请号：US10696775

申请日：2003-10-30

申请人： Masayuki Furuhashi ,  Toshifumi Mori ,  Young Suk Kim ,  Takayuki Ohba ,  Ryou Nakamura

发明人： Masayuki Furuhashi ,  Toshifumi Mori ,  Young Suk Kim ,  Takayuki Ohba ,  Ryou Nakamura

IPC分类号： H01L21/471 ,  C23C16/34 ,  C23C16/36

CPC分类号： H01L21/823814 ,  H01L21/823842

摘要： The semiconductor device fabrication method comprises the step of forming gate electrode 20 on a semiconductor substrate 10 with a gate insulation film 18 formed therebetween; the step of implanting dopants in the semiconductor substrate 10 with the gate electrode 20 as the mask to form dopant diffused regions 28, 36; the step of forming a silicon oxide film 38 on the semiconductor substrate 10, covering the gate electrodes 20; anisotropically etching the silicon oxide film 38 to form sidewall spacers 42 including the silicon oxide film 38 on the side walls of the gate electrode 20. In the step of forming a silicon oxide film 38, the silicon oxide film 38 is formed by thermal CVD at a 500–580° C. film forming temperature, using bis(tertiary-butylamino)silane and oxygen as raw materials. Silicon oxide film 38 is formed at a relatively low film forming temperature, whereby the diffusion of the dopant in the doapnt diffused regions 28, 36 forming the shallow region of the extension source/drain structure can be suppressed.

摘要翻译： 半导体器件制造方法包括在半导体衬底10上形成栅电极20的步骤，其间形成有栅极绝缘膜18; 以栅电极20为掩模，在半导体衬底10中注入掺杂剂以形成掺杂剂扩散区域28,36的步骤; 在半导体衬底10上形成覆盖栅电极20的氧化硅膜38的步骤; 各向异性地蚀刻氧化硅膜38以在栅电极20的侧壁上形成包括氧化硅膜38的侧壁间隔物42。 在形成氧化硅膜38的步骤中，使用双（叔丁基氨基）硅烷和氧气作为原料，通过热CVD在500-580℃成膜温度下形成氧化硅膜38。 在相对较低的成膜温度下形成氧化硅膜38，由此可以抑制形成扩展源极/漏极结构的浅区域的多个扩散区域28,36中的掺杂剂的扩散。

公开(公告)号：US07037803B2

公开(公告)日：2006-05-02

申请号：US10721870

申请日：2003-11-26

申请人： Kengo Inoue ,  Toshifumi Mori ,  Ryou Nakamura ,  Hiroyuki Ohta ,  Takashi Saiki

发明人： Kengo Inoue ,  Toshifumi Mori ,  Ryou Nakamura ,  Hiroyuki Ohta ,  Takashi Saiki

IPC分类号： H01L21/76

CPC分类号： H01L21/76224 ,  H01L21/823871 ,  H01L21/823878

摘要： A semiconductor device manufacture method has the steps of: (a) forming a polishing stopper layer over a semiconductor substrate; (b) etching the semiconductor substrate to form a trench; (c) forming a first liner insulating layer of silicon oxide over the surface of the trench; (d) forming a second liner insulating layer of silicon nitride over the first liner insulating layer, the second liner insulating layer having a thickness of at least 20 nm or at most 8 nm; (e1) depositing a third liner insulating layer of silicon oxide over the second liner insulating layer by plasma CVD at a first bias; and (e2) depositing an isolation layer of silicon oxide by plasma CVD at a second bias higher than the first bias, the isolation layer burying a recess defined by the third liner insulating layer.

摘要翻译： 半导体器件制造方法具有以下步骤：（a）在半导体衬底上形成抛光阻挡层; （b）蚀刻半导体衬底以形成沟槽; （c）在所述沟槽的表面上形成氧化硅的第一衬垫绝缘层; （d）在所述第一衬垫绝缘层上形成氮化硅的第二衬垫绝缘层，所述第二衬垫绝缘层的厚度为至少20nm或至多8nm; （e1）在第一偏压下通过等离子体CVD沉积第二衬里绝缘层上的第三衬垫绝缘层氧化硅; 和（e2）以高于第一偏压的第二偏压通过等离子体CVD沉积氧化硅隔离层，隔离层埋设由第三衬里绝缘层限定的凹部。

公开(公告)号：US07345003B2

公开(公告)日：2008-03-18

申请号：US11120981

申请日：2005-05-04

申请人： Takae Sukegawa ,  Ryou Nakamura

发明人： Takae Sukegawa ,  Ryou Nakamura

IPC分类号： H01L21/26

CPC分类号： H01L21/31111 ,  H01L21/324 ,  H01L21/67115

摘要： A semiconductor device manufacturing method capable of making in-plane temperature distribution on a wafer uniform at heat treatment time. Before heat treatment is performed by irradiating the wafer with lamp light from the side of a device formed area where semiconductor devices are to be formed, an SiN film with certain thickness the reflection factor of which is equal to the average reflection factor of the device formed area is formed in an edge portion outside the device formed area. By doing so, reflection factors on the surface of the wafer irradiated with lamp light can be made uniform and uniform temperature distribution on the wafer can be obtained at heat treatment time. As a result, in-plane variations in the characteristics of semiconductor devices on the wafer can be made small and high-quality semiconductor devices can be manufactured.

摘要翻译： 一种半导体器件制造方法，其能够使晶片的面内温度分布在热处理时间内均匀。 在通过从形成有半导体器件的器件形成区域的一侧的灯光照射晶片来进行热处理之前，具有一定厚度的SiN膜，其反射系数等于所形成的器件的平均反射系数 区域形成在装置形成区域外的边缘部分。 通过这样做，可以使用灯光照射的晶片的表面上的反射系数均匀，并且可以在热处理时间获得在晶片上均匀的温度分布。 结果，可以使晶片上的半导体器件的特性的面内变化小，并且可以制造高质量的半导体器件。

公开(公告)号：US07294577B2

公开(公告)日：2007-11-13

申请号：US11088984

申请日：2005-03-24

申请人： Junji Oh ,  Yuka Hayami ,  Ryou Nakamura

发明人： Junji Oh ,  Yuka Hayami ,  Ryou Nakamura

IPC分类号： H01L21/311

CPC分类号： H01L21/02052 ,  H01L21/26586 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864

摘要： There is provided a method of manufacturing semiconductor device comprising removing an organic substance from a semiconductor surface having an oxide film thereon, the semiconductor surface being formed to have a line width of 50 nm or less; removing the oxide film from the semiconductor surface; drying the semiconductor surface without using an organic solvent; and forming a silicide layer on the semiconductor surface after drying the semiconductor surface.

摘要翻译： 提供了一种制造半导体器件的方法，包括从其上具有氧化膜的半导体表面除去有机物质，半导体表面形成为具有50nm或更小的线宽度; 从半导体表面去除氧化膜; 干燥半导体表面而不使用有机溶剂; 以及在半导体表面干燥之后在半导体表面上形成硅化物层。

公开(公告)号：US20060141801A1

公开(公告)日：2006-06-29

申请号：US11120981

申请日：2005-05-04

申请人： Takae Sukegawa ,  Ryou Nakamura

发明人： Takae Sukegawa ,  Ryou Nakamura

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/31111 ,  H01L21/324 ,  H01L21/67115

摘要： A semiconductor device manufacturing method capable of making in-plane temperature distribution on a wafer uniform at heat treatment time. Before heat treatment is performed by irradiating the wafer with lamp light from the side of a device formed area where semiconductor devices are to be formed, an SiN film with certain thickness the reflection factor of which is equal to the average reflection factor of the device formed area is formed in an edge portion outside the device formed area. By doing so, reflection factors on the surface of the wafer irradiated with lamp light can be made uniform and uniform temperature distribution on the wafer can be obtained at heat treatment time. As a result, in-plane variations in the characteristics of semiconductor devices on the wafer can be made small and high-quality semiconductor devices can be manufactured.

摘要翻译： 一种半导体器件制造方法，其能够使晶片的面内温度分布在热处理时间内均匀。 在通过从形成有半导体器件的器件形成区域的一侧的灯光照射晶片来进行热处理之前，具有一定厚度的SiN膜，其反射系数等于所形成的器件的平均反射系数 区域形成在装置形成区域外的边缘部分。 通过这样做，可以使用灯光照射的晶片的表面上的反射系数均匀，并且可以在热处理时间获得在晶片上均匀的温度分布。 结果，可以使晶片上的半导体器件的特性的面内变化小，并且可以制造高质量的半导体器件。

公开(公告)号：US20050215003A1

公开(公告)日：2005-09-29

申请号：US11088984

申请日：2005-03-24

申请人： Junji Oh ,  Yuka Hayami ,  Ryou Nakamura

发明人： Junji Oh ,  Yuka Hayami ,  Ryou Nakamura

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L21/02052 ,  H01L21/26586 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864

摘要： There is provided a method of manufacturing semiconductor device comprising removing an organic substance from a semiconductor surface having an oxide film thereon, the semiconductor surface being formed to have a line width of 50 nm or less; removing the oxide film from the semiconductor surface; drying the semiconductor surface without using an organic solvent; and forming a silicide layer on the semiconductor surface after drying the semiconductor surface.

摘要翻译： 提供了一种制造半导体器件的方法，包括从其上具有氧化膜的半导体表面除去有机物质，半导体表面形成为具有50nm或更小的线宽度; 从半导体表面去除氧化膜; 干燥半导体表面而不使用有机溶剂; 以及在半导体表面干燥之后在半导体表面上形成硅化物层。

公开(公告)号：US07859088B2

公开(公告)日：2010-12-28

申请号：US12010142

申请日：2008-01-22

申请人： Takae Sukegawa ,  Ryou Nakamura

发明人： Takae Sukegawa ,  Ryou Nakamura

IPC分类号： H01L23/58

CPC分类号： H01L21/31111 ,  H01L21/324 ,  H01L21/67115

摘要： A semiconductor device manufacturing method capable of making in-plane temperature distribution on a wafer uniform at heat treatment time. Before heat treatment is performed by irradiating the wafer with lamp light from the side of a device formed area where semiconductor devices are to be formed, an SiN film with certain thickness the reflection factor of which is equal to the average reflection factor of the device formed area is formed in an edge portion outside the device formed area. By doing so, reflection factors on the surface of the wafer irradiated with lamp light can be made uniform and uniform temperature distribution on the wafer can be obtained at heat treatment time. As a result, in-plane variations in the characteristics of semiconductor devices on the wafer can be made small and high-quality semiconductor devices can be manufactured.

摘要翻译： 一种半导体器件制造方法，其能够使晶片的面内温度分布在热处理时间内均匀。 在通过从形成有半导体器件的器件形成区域的一侧的灯光照射晶片来进行热处理之前，具有一定厚度的SiN膜，其反射系数等于所形成的器件的平均反射系数 区域形成在装置形成区域外的边缘部分。 通过这样做，可以使用灯光照射的晶片的表面上的反射系数均匀，并且可以在热处理时间获得在晶片上均匀的温度分布。 结果，可以使晶片上的半导体器件的特性的面内变化小，并且可以制造高质量的半导体器件。

公开(公告)号：US20080122046A1

公开(公告)日：2008-05-29

申请号：US12010142

申请日：2008-01-22

申请人： Takae Sukegawa ,  Ryou Nakamura

发明人： Takae Sukegawa ,  Ryou Nakamura

IPC分类号： H01L23/58

CPC分类号： H01L21/31111 ,  H01L21/324 ,  H01L21/67115

摘要： A semiconductor device manufacturing method capable of making in-plane temperature distribution on a wafer uniform at heat treatment time. Before heat treatment is performed by irradiating the wafer with lamp light from the side of a device formed area where semiconductor devices are to be formed, an SiN film with certain thickness the reflection factor of which is equal to the average reflection factor of the device formed area is formed in an edge portion outside the device formed area. By doing so, reflection factors on the surface of the wafer irradiated with lamp light can be made uniform and uniform temperature distribution on the wafer can be obtained at heat treatment time. As a result, in-plane variations in the characteristics of semiconductor devices on the wafer can be made small and high-quality semiconductor devices can be manufactured.

公开(公告)号：US20060079087A1

公开(公告)日：2006-04-13

申请号：US11041217

申请日：2005-01-25

申请人： Kazuo Kawamura ,  Satoshi Inagaki ,  Takashi Saiki ,  Ryou Nakamura

发明人： Kazuo Kawamura ,  Satoshi Inagaki ,  Takashi Saiki ,  Ryou Nakamura

IPC分类号： H01L21/44 ,  H01L21/4763 ,  H01L21/336

CPC分类号： H01L21/02186 ,  H01L21/26513 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/318 ,  H01L29/4933 ,  H01L29/665

摘要： A method of producing a semiconductor device is disclosed that is able to reduce fluctuations of a sheet resistance of a silicide layer in the semiconductor device formed by a salicide process. When depositing a titanium nitride film on a cobalt film in the salicide process, the thickness of the titanium nitride film is set to be sufficiently small so that a nano-grain structure or an amorphous structure is formed in the titanium nitride film. In the titanium nitride film, the titanium composition is enriched.

摘要翻译： 公开了一种制造半导体器件的方法，其能够减少通过自对准硅化物工艺形成的半导体器件中的硅化物层的薄层电阻的波动。 当在自对准硅化物工艺中在钴膜上沉积氮化钛膜时，将氮化钛膜的厚度设定得足够小，使得在氮化钛膜中形成纳米晶粒结构或非晶结构。 在氮化钛膜中，钛组合物富集。