公开(公告)号：US07166516B2

公开(公告)日：2007-01-23

申请号：US10696775

申请日：2003-10-30

申请人： Masayuki Furuhashi ,  Toshifumi Mori ,  Young Suk Kim ,  Takayuki Ohba ,  Ryou Nakamura

发明人： Masayuki Furuhashi ,  Toshifumi Mori ,  Young Suk Kim ,  Takayuki Ohba ,  Ryou Nakamura

IPC分类号： H01L21/471 ,  C23C16/34 ,  C23C16/36

CPC分类号： H01L21/823814 ,  H01L21/823842

摘要： The semiconductor device fabrication method comprises the step of forming gate electrode 20 on a semiconductor substrate 10 with a gate insulation film 18 formed therebetween; the step of implanting dopants in the semiconductor substrate 10 with the gate electrode 20 as the mask to form dopant diffused regions 28, 36; the step of forming a silicon oxide film 38 on the semiconductor substrate 10, covering the gate electrodes 20; anisotropically etching the silicon oxide film 38 to form sidewall spacers 42 including the silicon oxide film 38 on the side walls of the gate electrode 20. In the step of forming a silicon oxide film 38, the silicon oxide film 38 is formed by thermal CVD at a 500–580° C. film forming temperature, using bis(tertiary-butylamino)silane and oxygen as raw materials. Silicon oxide film 38 is formed at a relatively low film forming temperature, whereby the diffusion of the dopant in the doapnt diffused regions 28, 36 forming the shallow region of the extension source/drain structure can be suppressed.

摘要翻译： 半导体器件制造方法包括在半导体衬底10上形成栅电极20的步骤，其间形成有栅极绝缘膜18; 以栅电极20为掩模，在半导体衬底10中注入掺杂剂以形成掺杂剂扩散区域28,36的步骤; 在半导体衬底10上形成覆盖栅电极20的氧化硅膜38的步骤; 各向异性地蚀刻氧化硅膜38以在栅电极20的侧壁上形成包括氧化硅膜38的侧壁间隔物42。 在形成氧化硅膜38的步骤中，使用双（叔丁基氨基）硅烷和氧气作为原料，通过热CVD在500-580℃成膜温度下形成氧化硅膜38。 在相对较低的成膜温度下形成氧化硅膜38，由此可以抑制形成扩展源极/漏极结构的浅区域的多个扩散区域28,36中的掺杂剂的扩散。

公开(公告)号：US20070072381A1

公开(公告)日：2007-03-29

申请号：US11606271

申请日：2006-11-30

申请人： Masayuki Furuhashi ,  Toshifumi Mori ,  Young Kim ,  Takayuki Ohba ,  Ryou Nakamura

发明人： Masayuki Furuhashi ,  Toshifumi Mori ,  Young Kim ,  Takayuki Ohba ,  Ryou Nakamura

IPC分类号： H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/823842

摘要： The semiconductor device fabrication method comprises the step of forming gate electrode 20 on a semiconductor substrate 10 with a gate insulation film 18 formed therebetween; the step of implanting dopants in the semiconductor substrate 10 with the gate electrode 20 as the mask to form dopant diffused regions 28, 36; the step of forming a silicon oxide film 38 on the semiconductor substrate 10, covering the gate electrodes 20; anisotropically etching the silicon oxide film 38 to form sidewall spacers 42 including the silicon oxide film 38 on the side walls of the gate electrode 20. In the step of forming a silicon oxide film 38, the silicon oxide film 38 is formed by thermal CVD at a 500-580° C. film forming temperature, using bis (tertiary-butylamino) silane and oxygen as raw materials. Silicon oxide film 38 is formed at a relatively low film forming temperature, whereby the diffusion of the dopant in the dopant diffused regions 28, 36 forming the shallow region of the extension source/drain structure can be suppressed.

摘要翻译： 半导体器件制造方法包括在半导体衬底10上形成栅电极20的步骤，其间形成有栅极绝缘膜18; 以栅电极20为掩模，在半导体衬底10中注入掺杂剂以形成掺杂剂扩散区域28,36的步骤; 在半导体衬底10上形成覆盖栅电极20的氧化硅膜38的步骤; 各向异性地蚀刻氧化硅膜38以在栅电极20的侧壁上形成包括氧化硅膜38的侧壁间隔物42。 在形成氧化硅膜38的步骤中，使用双（叔丁基氨基）硅烷和氧气作为原料，通过热CVD在500-580℃成膜温度下形成氧化硅膜38。 在相对低的成膜温度下形成氧化硅膜38，由此能够抑制形成扩展源极/漏极结构的浅区域的掺杂剂扩散区域28,36中的掺杂剂的扩散。

公开(公告)号：US4804560A

公开(公告)日：1989-02-14

申请号：US026900

申请日：1987-03-17

申请人： Yoshimi Shioya ,  Yasushi Oyama ,  Norihisa Tsuzuki ,  Mamoru Maeda ,  Masaaki Ichikawa ,  Fumitake Mieno ,  Shin-ichi Inoue ,  Yasuo Uo-ochi ,  Akira Tabuchi ,  Atsuhiro Tsukune ,  Takuya Watanabe ,  Takayuki Ohba

发明人： Yoshimi Shioya ,  Yasushi Oyama ,  Norihisa Tsuzuki ,  Mamoru Maeda ,  Masaaki Ichikawa ,  Fumitake Mieno ,  Shin-ichi Inoue ,  Yasuo Uo-ochi ,  Akira Tabuchi ,  Atsuhiro Tsukune ,  Takuya Watanabe ,  Takayuki Ohba

IPC分类号： H01L21/205 ,  C23C16/04 ,  C23C16/14 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  B05D5/12 ,  C23C16/00

CPC分类号： H01L21/28562 ,  H01L21/32051 ,  H01L21/76879

摘要： A method of selectively depositing tungsten upon a silicon semiconductor substrate. A silicon substrate is coated with a masking film of PSG or SiO.sub.2 that is patterned to provide an opening for forming an electrode or wiring. On a portion of the substrate in the opening, a layer of tungsten having a thickness of approximately 2000 .ANG. is deposited by a CVD method from an atomosphere containing a gaseous mixture of WF.sub.6 and H.sub.2 . During this processing, tungsten nucleuses deposit on the surface of the masking film as well. Before such nucleuses form a film, the deposition processing is discontinued and H.sub.2 gas is fed into the CVD apparatus to produce HF, which etches the surface of the masking film, and thus tungsten nucleuses are removed. The deposition and removal steps are repeated several times until the height of the deposited tungsten and the thickness of the masking film are essentially equal to present a flat surface. Aluminum film is deposited on the flat surface and patterned by lithography. The flat aluminum deposition allows fabrication of accurate and reliable wirings and facilitates production of VLSI of sub-micron order.

摘要翻译： 一种在硅半导体衬底上选择性地沉积钨的方法。 硅衬底涂覆有被图案化以提供用于形成电极或布线的开口的PSG或SiO 2的掩模膜。 在开口中的基板的一部分上，通过CVD法从含有WF6和H2的气体混合物的大气层沉积厚度约为2000的钨层。 在该处理中，钨核沉积在掩模膜的表面上也是如此。 在这种核形成膜之前，中断沉积处理，并且将H 2气体进料到CVD装置中以产生HF，其蚀刻掩模膜的表面，因此除去钨原子。 沉积和去除步骤重复几次，直到沉积的钨的高度和掩模膜的厚度基本上等于呈现平坦表面。 铝膜沉积在平坦表面上并通过光刻图案化。 扁平铝沉积允许制造准确可靠的布线，并有助于生产亚微米级VLSI。

公开(公告)号：US09748217B2

公开(公告)日：2017-08-29

申请号：US14003288

申请日：2012-03-08

申请人： Takayuki Ohba

发明人： Takayuki Ohba

IPC分类号： H01L21/00 ,  H01L25/00 ,  H01L23/31 ,  H01L23/48 ,  H01L21/768 ,  H01L25/065 ,  H01L21/683 ,  H01L21/56 ,  H01L23/544

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/544 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2924/1461 ,  H01L2924/00

摘要： A semiconductor device production method where separate semiconductor chips are stacked on a semiconductor substrate having a main surface on which multiple semiconductor chips including semiconductor integrated circuits are formed, the semiconductor chips in different layers are connected to each other to enable signal transmission, and a structure formed thereby is separated into multiple stacks of the semiconductor chips. The method includes a first step of forming an insulating layer on the main surface of the semiconductor substrate; a second step of stacking the separate semiconductor chips, which include the integrated semiconductor circuits on main surfaces thereof, via the insulating layer on the semiconductor chips formed on the semiconductor substrate such that opposite surfaces of the separate semiconductor chips opposite to the main surfaces face the insulating layer; and a third step of forming connecting parts that enable signal transmission between the semiconductor chips in different layers.

公开(公告)号：US20130344655A1

公开(公告)日：2013-12-26

申请号：US14003288

申请日：2012-03-08

申请人： Takayuki Ohba

发明人： Takayuki Ohba

IPC分类号： H01L25/00

CPC分类号： H01L25/50 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/544 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2924/1461 ,  H01L2924/00

摘要： A semiconductor device production method where separate semiconductor chips are stacked on a semiconductor substrate having a main surface on which multiple semiconductor chips including semiconductor integrated circuits are formed, the semiconductor chips in different layers are connected to each other to enable signal transmission, and a structure formed thereby is separated into multiple stacks of the semiconductor chips. The method includes a first step of forming an insulating layer on the main surface of the semiconductor substrate; a second step of stacking the separate semiconductor chips, which include the integrated semiconductor circuits on main surfaces thereof, via the insulating layer on the semiconductor chips formed on the semiconductor substrate such that opposite surfaces of the separate semiconductor chips opposite to the main surfaces face the insulating layer; and a third step of forming connecting parts that enable signal transmission between the semiconductor chips in different layers.

摘要翻译： 一种半导体器件制造方法，其中分离的半导体芯片堆叠在具有形成有包括半导体集成电路的多个半导体芯片的主表面的半导体衬底上，不同层中的半导体芯片彼此连接以实现信号传输，并且结构 由此形成的半导体芯片分成多个堆叠。 该方法包括在半导体衬底的主表面上形成绝缘层的第一步骤; 在半导体衬底上形成的半导体芯片上的绝缘层将包含集成半导体电路的分离的半导体芯片堆叠在半导体衬底上的第二步骤，使得与主表面相对的分离的半导体芯片的相对表面面向 绝缘层; 以及形成能够在不同层中的半导体芯片之间进行信号传输的连接部分的第三步骤。

公开(公告)号：US20050282400A1

公开(公告)日：2005-12-22

申请号：US11135648

申请日：2005-05-24

申请人： Shiqin Xiao ,  Takayuki Ohba

发明人： Shiqin Xiao ,  Takayuki Ohba

IPC分类号： C23C14/06 ,  C23C16/30 ,  C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  C23C16/56 ,  H01L21/02 ,  H01L21/20 ,  H01L21/28 ,  H01L21/31 ,  H01L21/314 ,  H01L21/316 ,  H01L21/469 ,  H01L29/51

CPC分类号： H01L21/0228 ,  C23C14/0641 ,  C23C16/308 ,  C23C16/405 ,  C23C16/45527 ,  C23C16/45529 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/0234 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/3141 ,  H01L21/3142 ,  H01L21/3143 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method of forming a dielectric film on a substrate surface includes the steps of forming the dielectric film on the substrate surface in plural steps, and reforming, in each of the plural steps of forming the dielectric film, the dielectric film in an ambient primarily of nitrogen.

摘要翻译： 在基板表面上形成电介质膜的方法包括以下步骤：在基板表面上形成多个阶段的电介质膜，并且在形成电介质膜的多个步骤中的每个步骤中，在绝缘膜主要为 氮。

公开(公告)号：USRE36925E

公开(公告)日：2000-10-31

申请号：US88377

申请日：1998-06-02

申请人： Takayuki Ohba ,  Toshiya Suzuki ,  Seishi Murakami

发明人： Takayuki Ohba ,  Toshiya Suzuki ,  Seishi Murakami

IPC分类号： H01L21/205 ,  C23C16/44 ,  H01L21/00 ,  H01L21/285 ,  H01L21/304 ,  H01L21/31 ,  B08B3/10

CPC分类号： H01L21/67167 ,  H01L21/67051 ,  H01L21/67109 ,  H01L21/67126 ,  H01L21/6719 ,  Y10S134/902

摘要： When an object of treatment is subjected to, for example, a gas treatment in an airtight chamber, reaction products adhere to the inner wall surface of the chamber, an object holder therein, and the corner portions of the chamber. When a cleaning medium is injected into the chamber, according to the present invention, the reaction products are dissolved in the cleaning medium by hydrolysis. Thereafter, the cleaning medium is discharged from the chamber. Then, the chamber is heated and evacuated, so that water vapor is discharged to provide a predetermined degree of vacuum, whereupon the treatment can be started anew. Therefore, a wiping operation can be omitted. Moreover, the reaction products remaining at the corner portions of the chamber can be removed without forming a source of polluted particles, so that the necessity of overhauling can be obviated. Thus, fully automatic cleaning, so to speak, can be effected, and the chamber need not be open to the atmosphere, so that the throughput can be improved.

摘要翻译： 当处理对象例如在气密室中进行气体处理时，反应产物粘附到室的内壁表面，物体保持器和腔室的角部。 当将清洁介质注入室中时，根据本发明，反应产物通过水解溶解在清洁介质中。 此后，清洗介质从室排出。 然后，对该室进行加热抽真空，从而排出水蒸气以提供预定的真空度，从而重新开始处理。 因此，可以省略擦拭操作。 此外，残留在室的角部的反应产物可以被除去而不形成污染颗粒源，从而可以消除大修的必要性。 因此，可以实现全自动清洗，并且室不需要对大气开放，从而可以提高生产量。

公开(公告)号：US07279790B2

公开(公告)日：2007-10-09

申请号：US10105286

申请日：2002-03-26

申请人： Hideki Kitada ,  Noriyoshi Shimizu ,  Nobuyuki Ohtsuka ,  Takayuki Ohba

发明人： Hideki Kitada ,  Noriyoshi Shimizu ,  Nobuyuki Ohtsuka ,  Takayuki Ohba

IPC分类号： H01L23/48

CPC分类号： H01L21/76843 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

摘要： A multilayer interconnection structure that offers a fast semiconductor operation is realized by employing copper wiring, electro migration of which is prevented from occurring by providing a via plug that includes a layer of a high melting-point metal, such as tungsten.

摘要翻译： 通过采用铜布线实现提供快速半导体操作的多层互连结构，通过提供包括诸如钨的高熔点金属层的通孔来防止其电迁移。

公开(公告)号：US06998303B2

公开(公告)日：2006-02-14

申请号：US10633534

申请日：2003-08-05

申请人： Yoshihiro Sugita ,  Yusuke Morisaki ,  Kiyoshi Irino ,  Shiqin Xiao ,  Takayuki Ohba

发明人： Yoshihiro Sugita ,  Yusuke Morisaki ,  Kiyoshi Irino ,  Shiqin Xiao ,  Takayuki Ohba

IPC分类号： H01L21/76

CPC分类号： H01L21/823857 ,  H01L21/265 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31122 ,  H01L21/31604 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： An insulating film made of zirconia or hafnia is formed on the surface of a semiconductor substrate. A partial surface area of the insulating film is covered with a mask pattern. By using the mask pattern as a mask, ions are implanted into a region of the insulating film not covered with the mask pattern to give damages to the insulating film. By using the mask pattern as a mask, a portion of the insulating film is etched.

摘要翻译： 在半导体衬底的表面上形成由氧化锆或铪形成的绝缘膜。 绝缘膜的部分表面积被掩模图案覆盖。 通过使用掩模图案作为掩模，将离子注入到未被掩模图案覆盖的绝缘膜的区域中，以对绝缘膜造成损害。 通过使用掩模图案作为掩模，蚀刻绝缘膜的一部分。

公开(公告)号：US06355545B1

公开(公告)日：2002-03-12

申请号：US09539710

申请日：2000-03-31

申请人： Takayuki Ohba

发明人： Takayuki Ohba

IPC分类号： H01L2128

CPC分类号： H01L21/76871 ,  H01L21/28556 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  H01L2221/1089

摘要： The present invention provides a method for wiring, which plugs conductive material sufficiently into a via hole produced in dielectronics (hereinafter, referred to as “a via hole”) and prevents generating a void. The via hole is made through a via hole patterning step and a cleaning step. At a surface treatment step, substance having chemical affinity (active site) is adsorbed to the surface of the via hole. Next, an electron donative layer is made by depositing substance having an electron donative characteristic on the active sites acting as cores at an electron donative layer formation step. Then, the wiring material is plugged at a via hole plug step.

摘要翻译： 本发明提供了一种布线方法，其将导电材料充分地插入到在电介质中产生的通孔中（以下称为“通孔”），并且防止产生空隙。 通孔通过通孔图案化步骤和清洁步骤制成。 在表面处理步骤中，具有化学亲和性（活性位点）的物质被吸附到通孔的表面。 接下来，通过在作为电子给体层形成步骤的核心的活性部位上沉积具有电子给体特性的物质来制造给电子层。 然后，布线材料在通孔插塞步骤中被插入。