公开(公告)号：US08120089B2

公开(公告)日：2012-02-21

申请号：US12650076

申请日：2009-12-30

申请人： Young-Hoo Kim ,  Daehyuk Kang ,  Youngok Kim ,  Sang Won Bae ,  Boun Yoon ,  Kuntack Lee

发明人： Young-Hoo Kim ,  Daehyuk Kang ,  Youngok Kim ,  Sang Won Bae ,  Boun Yoon ,  Kuntack Lee

IPC分类号： H01L29/76

CPC分类号： H01L29/792 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： Provided are nonvolatile memory devices with a three-dimensional structure and methods of fabricating the same. The nonvolatile memory device includes conductive patterns three-dimensionally arranged on a semiconductor substrate, semiconductor patterns that extend from the semiconductor substrate and intersect one-side walls of the conductive patterns, charge storage layers interposed between the semiconductor patterns and one-side walls of the conductive patterns, and seed layer patterns interposed between the charge storage layers and one-side walls of the conductive patterns.

摘要翻译： 提供具有三维结构的非易失性存储器件及其制造方法。 非易失性存储器件包括三维地布置在半导体衬底上的导电图案，半导体图案从半导体衬底延伸并与导电图案的一侧壁相交，插入在半导体图案和半导体图案的一侧壁之间的电荷存储层 导电图案和介于电荷存储层和导电图案的单侧壁之间的种子层图案。

公开(公告)号：US20100181610A1

公开(公告)日：2010-07-22

申请号：US12650076

申请日：2009-12-30

申请人： Young-Hoo Kim ,  Daehyuk Kang ,  Youngok Kim ,  Sang Won Bae ,  Boun Yoon ,  Kuntack Lee

发明人： Young-Hoo Kim ,  Daehyuk Kang ,  Youngok Kim ,  Sang Won Bae ,  Boun Yoon ,  Kuntack Lee

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： Provided are nonvolatile memory devices with a three-dimensional structure and methods of fabricating the same. The nonvolatile memory device includes conductive patterns three-dimensionally arranged on a semiconductor substrate, semiconductor patterns that extend from the semiconductor substrate and intersect one-side walls of the conductive patterns, charge storage layers interposed between the semiconductor patterns and one-side walls of the conductive patterns, and seed layer patterns interposed between the charge storage layers and one-side walls of the conductive patterns.

摘要翻译： 提供具有三维结构的非易失性存储器件及其制造方法。 非易失性存储器件包括三维地布置在半导体衬底上的导电图案，半导体图案从半导体衬底延伸并与导电图案的一侧壁相交，插入在半导体图案和半导体图案的一侧壁之间的电荷存储层 导电图案和介于电荷存储层和导电图案的单侧壁之间的种子层图案。

公开(公告)号：US08076198B2

公开(公告)日：2011-12-13

申请号：US12657092

申请日：2010-01-13

申请人： Hyosan Lee ,  Boun Yoon ,  Kuntack Lee ,  Donghyun Kim ,  Daehyuk Kang ,  Imsoo Park ,  Youngok Kim ,  Young-Hoo Kim ,  Sang Won Bae

发明人： Hyosan Lee ,  Boun Yoon ,  Kuntack Lee ,  Donghyun Kim ,  Daehyuk Kang ,  Imsoo Park ,  Youngok Kim ,  Young-Hoo Kim ,  Sang Won Bae

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/4763 ,  H01L21/461

CPC分类号： H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/7881

摘要： A method of fabricating a nonvolatile memory device with a three-dimensional structure includes alternately stacking first and second material layers in two or more layers on a semiconductor substrate, forming trenches penetrating the stacked first and second material layers by performing a first etching process, and removing the second material layers exposed in the trenches by performing a second etching process. The first and second material layers are formed of materials that have the same main component but have different impurity contents, respectively.

摘要翻译： 一种制造具有三维结构的非易失性存储器件的方法包括在半导体衬底上交替堆叠两层或多层第一和第二材料层，通过执行第一蚀刻工艺形成贯穿层叠的第一和第二材料层的沟槽，以及 通过执行第二蚀刻工艺去除在沟槽中暴露的第二材料层。 第一和第二材料层由具有相同主要成分但具有不同杂质含量的材料形成。

公开(公告)号：US20100178755A1

公开(公告)日：2010-07-15

申请号：US12657092

申请日：2010-01-13

申请人： Hyosan Lee ,  Boun Yoon ,  Kuntack Lee ,  Donghyun Kim ,  Daehyuk Kang ,  Imsoo Park ,  Youngok Kim ,  Young-Hoo Kim ,  Sang Won Bae

发明人： Hyosan Lee ,  Boun Yoon ,  Kuntack Lee ,  Donghyun Kim ,  Daehyuk Kang ,  Imsoo Park ,  Youngok Kim ,  Young-Hoo Kim ,  Sang Won Bae

IPC分类号： H01L21/20

CPC分类号： H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/7881

摘要： A method of fabricating a nonvolatile memory device with a three-dimensional structure includes alternately stacking first and second material layers in two or more layers on a semiconductor substrate, forming trenches penetrating the stacked first and second material layers by performing a first etching process, and removing the second material layers exposed in the trenches by performing a second etching process. The first and second material layers are formed of materials that have the same main component but have different impurity contents, respectively.

摘要翻译： 一种制造具有三维结构的非易失性存储器件的方法包括在半导体衬底上交替堆叠两层或多层第一和第二材料层，通过执行第一蚀刻工艺形成贯穿层叠的第一和第二材料层的沟槽，以及 通过执行第二蚀刻工艺去除在沟槽中暴露的第二材料层。 第一和第二材料层由具有相同主要成分但具有不同杂质含量的材料形成。

公开(公告)号：US20120003831A1

公开(公告)日：2012-01-05

申请号：US13173591

申请日：2011-06-30

申请人： Daehyuk Kang ,  Sang Won Bae ,  Boun Yoon ,  Kuntach Lee ,  Young-Hoo Kim

发明人： Daehyuk Kang ,  Sang Won Bae ,  Boun Yoon ,  Kuntach Lee ,  Young-Hoo Kim

IPC分类号： H01L21/8239

CPC分类号： H01L27/11578 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

摘要： Methods of forming nonvolatile memory devices include forming a stack of layers of different materials on a substrate. This stack includes a plurality of first layers of a first material and a plurality of second layers of a second material arranged in an alternating sequence of first and second layers. A selected first portion of the stack of layers is isotropically etched for a sufficient duration to define a first trench therein that exposes sidewalls of the alternating sequence of first and second layers. The sidewalls of each of the plurality of first layers are selectively etched relative to sidewalls of adjacent ones of the plurality of second layers. Another etching step is then performed to recess sidewalls of the plurality of second layers and thereby expose portions of upper surfaces of the plurality of first layers. These exposed portions of the upper surfaces of the plurality of first layers, which may act as word lines of a memory device, are displaced laterally relative to each other.

摘要翻译： 形成非易失性存储器件的方法包括在衬底上形成不同材料层的堆叠。 该堆叠包括以第一和第二层的交替顺序布置的多个第一材料的第一层和多个第二层的第二层。 各层的所选择的第一部分被各向同性蚀刻足够的持续时间以限定其中的第一沟槽的第一和第二层的交替序列的侧壁。 多个第一层中的每一个的侧壁相对于多个第二层中的相邻侧壁的侧壁被选择性地蚀刻。 然后执行另一蚀刻步骤以使多个第二层的侧壁凹陷，从而暴露多个第一层的上表面的部分。 可以充当存储器件的字线的多个第一层的上表面的这些暴露部分相对于彼此横向偏移。

公开(公告)号：US20100200431A1

公开(公告)日：2010-08-12

申请号：US12704206

申请日：2010-02-11

申请人： Youngok Kim ,  Jeongnam Han ,  Changki Hong ,  Boun Yoon ,  Kuntack Lee ,  Young-Hoo Kim

发明人： Youngok Kim ,  Jeongnam Han ,  Changki Hong ,  Boun Yoon ,  Kuntack Lee ,  Young-Hoo Kim

IPC分类号： G01N27/26

CPC分类号： H01L22/14

摘要： The inventive concept provides a wafer test method and a wafer test apparatus. The wafer test method can recognize the amount of residuals generated in a sidewall of the metal-containing layer pattern and the extent of corrosion of a sidewall of the metal-containing layer pattern using the measured electric resistance by supplying an electrolyte so that the electrolyte is in contact with a portion of the metal-containing layer pattern in a predetermined chip region and measuring an electric resistance between a first electrode which is electrically in contact with the other portion of the metal-containing layer pattern and a second electrode which is in contact with the electrolyte in the predetermined region. Thus, a wafer test method and a wafer test apparatus can be embodied by an in-line method without dividing a wafer into each chip.

摘要翻译： 本发明的概念提供了晶片测试方法和晶片测试装置。 晶片测试方法可以通过提供电解质来确定含金属层图案的侧壁中产生的残留量以及含金属层图案的侧壁的腐蚀程度，使得电解质为 与预定芯片区域中的含金属层图案的一部分接触，并且测量与含金属层图案的另一部分电接触的第一电极和接触的第二电极之间的电阻 电解液在预定区域内。 因此，可以通过在线方式来实现晶片测试方法和晶片测试装置，而不将晶片分成每个芯片。

公开(公告)号：US08228089B2

公开(公告)日：2012-07-24

申请号：US12704206

申请日：2010-02-11

申请人： Youngok Kim ,  Jeongnam Han ,  Changki Hong ,  Boun Yoon ,  Kuntack Lee ,  Young-Hoo Kim

发明人： Youngok Kim ,  Jeongnam Han ,  Changki Hong ,  Boun Yoon ,  Kuntack Lee ,  Young-Hoo Kim

IPC分类号： G01R31/26 ,  G01R31/08 ,  H01L21/66

CPC分类号： H01L22/14

摘要： The inventive concept provides a wafer test method and a wafer test apparatus. The wafer test method can recognize the amount of residuals generated in a sidewall of the metal-containing layer pattern and the extent of corrosion of a sidewall of the metal-containing layer pattern using the measured electric resistance by supplying an electrolyte so that the electrolyte is in contact with a portion of the metal-containing layer pattern in a predetermined chip region and measuring an electric resistance between a first electrode which is electrically in contact with the other portion of the metal-containing layer pattern and a second electrode which is in contact with the electrolyte in the predetermined region. Thus, a wafer test method and a wafer test apparatus can be embodied by an in-line method without dividing a wafer into each chip.

摘要翻译： 本发明的概念提供了晶片测试方法和晶片测试装置。 晶片测试方法可以通过提供电解质来确定含金属层图案的侧壁中产生的残留量以及含金属层图案的侧壁的腐蚀程度，使得电解质为 与预定芯片区域中的含金属层图案的一部分接触，并且测量与含金属层图案的另一部分电接触的第一电极和接触的第二电极之间的电阻 电解液在预定区域内。 因此，可以通过在线方式来实现晶片测试方法和晶片测试装置，而不将晶片分成每个芯片。

公开(公告)号：US08268710B2

公开(公告)日：2012-09-18

申请号：US12703071

申请日：2010-02-09

申请人： Byoungho Kwon ,  Boun Yoon ,  Daeik Kim ,  Sung-Min Cho

发明人： Byoungho Kwon ,  Boun Yoon ,  Daeik Kim ,  Sung-Min Cho

IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/28123 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/11546 ,  H01L27/11548 ,  H01L27/11575

摘要： A method for fabricating a semiconductor device includes providing a semiconductor substrate including a memory cell region and peripheral circuit regions. Gate electrodes including gate conductive patterns and capping patterns are formed on the memory cell region and the peripheral circuit regions. An interlayer dielectric covering the gate electrodes is formed. The interlayer dielectric is patterned to form first contact holes exposing the semiconductor substrate along side of the gate electrode in the memory cell region and second contact holes exposing a portion of the capping pattern in the peripheral circuit region such that a bottom surface of the second contact hole is spaced apart from a top surface of the gate conductive pattern. A first plug conductive layer is filled in the first contact holes and a second plug conductive layer is filled in the second contact holes. A planarizing process is performed to expose the capping patterns such that first contact plugs are formed in the memory cell region and second contact plugs are formed in the peripheral circuit region.

摘要翻译： 一种制造半导体器件的方法包括提供包括存储单元区域和外围电路区域的半导体衬底。 包括栅极导电图案和封盖图案的栅电极形成在存储单元区域和外围电路区域上。 形成覆盖栅电极的层间电介质。 图案化层间电介质以形成沿着存储单元区域中的栅极电极的侧面暴露半导体衬底的第一接触孔，以及露出外围电路区域中的封盖图案的一部分的第二接触孔，使得第二接触件的底表面 孔与栅极导电图案的顶表面间隔开。 第一插头导电层填充在第一接触孔中，第二插头导电层填充在第二接触孔中。 执行平面化处理以暴露封盖图案，使得在存储单元区域中形成第一接触插塞，并且在外围电路区域中形成第二接触插塞。

公开(公告)号：US08252675B2

公开(公告)日：2012-08-28

申请号：US12942763

申请日：2010-11-09

申请人： Jongwon Lee ,  Boun Yoon ,  Sang Yeob Han ,  Chae Lyoung Kim

发明人： Jongwon Lee ,  Boun Yoon ,  Sang Yeob Han ,  Chae Lyoung Kim

IPC分类号： H01L21/336 ,  H01L21/44 ,  H01L21/88 ,  H01L21/4763

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/7833

摘要： Provided is a method for manufacturing a MOS transistor. The method comprises providing a substrate having a first active region and a second active region; forming a dummy gate stack on the first active region and the second active region, the dummy gate stack comprising a gate dielectric layer and a dummy gate electrode; forming source/drain regions in the first active region and the second active region disposed at both sides of the dummy gate stack; forming a mold insulating layer on the source/drain region; removing the dummy gate electrode on the first active region to form a first trench on the mold insulating layer; forming a first metal pattern to form a second trench at a lower portion of the first trench, and removing the dummy gate electrode on the second active region to from a third trench on the mold insulating layer; and forming a second metal layer in the second trench and the third trench to form a first gate electrode on the first active region and a second gate electrode on the second active region.

摘要翻译： 提供一种用于制造MOS晶体管的方法。 该方法包括提供具有第一有源区和第二有源区的衬底; 在所述第一有源区和所述第二有源区上形成虚设栅极叠层，所述伪栅叠层包括栅介电层和虚栅极; 在所述第一有源区中形成源极/漏极区域和设置在所述伪栅极堆叠的两侧的所述第二有源区域; 在源/漏区上形成模绝缘层; 去除所述第一有源区上的所述伪栅电极以在所述模绝缘层上形成第一沟槽; 形成第一金属图案以在所述第一沟槽的下部形成第二沟槽，以及将所述第二有源区上的所述伪栅电极从所述模绝缘层上的第三沟槽移除; 以及在所述第二沟槽和所述第三沟槽中形成第二金属层，以在所述第一有源区上形成第一栅电极，在所述第二有源区上形成第二栅电极。

公开(公告)号：US20110136313A1

公开(公告)日：2011-06-09

申请号：US12942763

申请日：2010-11-09

申请人： Jongwon Lee ,  Boun Yoon ,  Sang Yeob Han ,  Chae Lyoung Kim

发明人： Jongwon Lee ,  Boun Yoon ,  Sang Yeob Han ,  Chae Lyoung Kim

IPC分类号： H01L21/28 ,  H01L21/8234

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/7833

摘要： Provided is a method for manufacturing a MOS transistor. The method comprises providing a substrate having a first active region and a second active region; forming a dummy gate stack on the first active region and the second active region, the dummy gate stack comprising a gate dielectric layer and a dummy gate electrode; forming source/drain regions in the first active region and the second active region disposed at both sides of the dummy gate stack; forming a mold insulating layer on the source/drain region; removing the dummy gate electrode on the first active region to form a first trench on the mold insulating layer; forming a first metal pattern to form a second trench at a lower portion of the first trench, and removing the dummy gate electrode on the second active region to from a third trench on the mold insulating layer; and forming a second metal layer in the second trench and the third trench to form a first gate electrode on the first active region and a second gate electrode on the second active region.

摘要翻译： 提供一种用于制造MOS晶体管的方法。 该方法包括提供具有第一有源区和第二有源区的衬底; 在所述第一有源区和所述第二有源区上形成虚设栅极叠层，所述伪栅叠层包括栅介电层和虚栅极; 在所述第一有源区中形成源极/漏极区域和设置在所述伪栅极堆叠的两侧的所述第二有源区域; 在源/漏区上形成模绝缘层; 去除所述第一有源区上的所述伪栅电极以在所述模绝缘层上形成第一沟槽; 形成第一金属图案以在所述第一沟槽的下部形成第二沟槽，以及将所述第二有源区上的所述伪栅电极从所述模绝缘层上的第三沟槽移除; 以及在所述第二沟槽和所述第三沟槽中形成第二金属层，以在所述第一有源区上形成第一栅电极，在所述第二有源区上形成第二栅电极。