公开(公告)号：US08076198B2

公开(公告)日：2011-12-13

申请号：US12657092

申请日：2010-01-13

申请人： Hyosan Lee ,  Boun Yoon ,  Kuntack Lee ,  Donghyun Kim ,  Daehyuk Kang ,  Imsoo Park ,  Youngok Kim ,  Young-Hoo Kim ,  Sang Won Bae

发明人： Hyosan Lee ,  Boun Yoon ,  Kuntack Lee ,  Donghyun Kim ,  Daehyuk Kang ,  Imsoo Park ,  Youngok Kim ,  Young-Hoo Kim ,  Sang Won Bae

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/4763 ,  H01L21/461

CPC分类号： H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/7881

摘要： A method of fabricating a nonvolatile memory device with a three-dimensional structure includes alternately stacking first and second material layers in two or more layers on a semiconductor substrate, forming trenches penetrating the stacked first and second material layers by performing a first etching process, and removing the second material layers exposed in the trenches by performing a second etching process. The first and second material layers are formed of materials that have the same main component but have different impurity contents, respectively.

摘要翻译： 一种制造具有三维结构的非易失性存储器件的方法包括在半导体衬底上交替堆叠两层或多层第一和第二材料层，通过执行第一蚀刻工艺形成贯穿层叠的第一和第二材料层的沟槽，以及 通过执行第二蚀刻工艺去除在沟槽中暴露的第二材料层。 第一和第二材料层由具有相同主要成分但具有不同杂质含量的材料形成。

公开(公告)号：US20100178755A1

公开(公告)日：2010-07-15

申请号：US12657092

申请日：2010-01-13

申请人： Hyosan Lee ,  Boun Yoon ,  Kuntack Lee ,  Donghyun Kim ,  Daehyuk Kang ,  Imsoo Park ,  Youngok Kim ,  Young-Hoo Kim ,  Sang Won Bae

发明人： Hyosan Lee ,  Boun Yoon ,  Kuntack Lee ,  Donghyun Kim ,  Daehyuk Kang ,  Imsoo Park ,  Youngok Kim ,  Young-Hoo Kim ,  Sang Won Bae

IPC分类号： H01L21/20

CPC分类号： H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/7881

摘要： A method of fabricating a nonvolatile memory device with a three-dimensional structure includes alternately stacking first and second material layers in two or more layers on a semiconductor substrate, forming trenches penetrating the stacked first and second material layers by performing a first etching process, and removing the second material layers exposed in the trenches by performing a second etching process. The first and second material layers are formed of materials that have the same main component but have different impurity contents, respectively.

摘要翻译： 一种制造具有三维结构的非易失性存储器件的方法包括在半导体衬底上交替堆叠两层或多层第一和第二材料层，通过执行第一蚀刻工艺形成贯穿层叠的第一和第二材料层的沟槽，以及 通过执行第二蚀刻工艺去除在沟槽中暴露的第二材料层。 第一和第二材料层由具有相同主要成分但具有不同杂质含量的材料形成。

公开(公告)号：US08120089B2

公开(公告)日：2012-02-21

申请号：US12650076

申请日：2009-12-30

申请人： Young-Hoo Kim ,  Daehyuk Kang ,  Youngok Kim ,  Sang Won Bae ,  Boun Yoon ,  Kuntack Lee

发明人： Young-Hoo Kim ,  Daehyuk Kang ,  Youngok Kim ,  Sang Won Bae ,  Boun Yoon ,  Kuntack Lee

IPC分类号： H01L29/76

CPC分类号： H01L29/792 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： Provided are nonvolatile memory devices with a three-dimensional structure and methods of fabricating the same. The nonvolatile memory device includes conductive patterns three-dimensionally arranged on a semiconductor substrate, semiconductor patterns that extend from the semiconductor substrate and intersect one-side walls of the conductive patterns, charge storage layers interposed between the semiconductor patterns and one-side walls of the conductive patterns, and seed layer patterns interposed between the charge storage layers and one-side walls of the conductive patterns.

摘要翻译： 提供具有三维结构的非易失性存储器件及其制造方法。 非易失性存储器件包括三维地布置在半导体衬底上的导电图案，半导体图案从半导体衬底延伸并与导电图案的一侧壁相交，插入在半导体图案和半导体图案的一侧壁之间的电荷存储层 导电图案和介于电荷存储层和导电图案的单侧壁之间的种子层图案。

公开(公告)号：US20100181610A1

公开(公告)日：2010-07-22

申请号：US12650076

申请日：2009-12-30

申请人： Young-Hoo Kim ,  Daehyuk Kang ,  Youngok Kim ,  Sang Won Bae ,  Boun Yoon ,  Kuntack Lee

发明人： Young-Hoo Kim ,  Daehyuk Kang ,  Youngok Kim ,  Sang Won Bae ,  Boun Yoon ,  Kuntack Lee

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： Provided are nonvolatile memory devices with a three-dimensional structure and methods of fabricating the same. The nonvolatile memory device includes conductive patterns three-dimensionally arranged on a semiconductor substrate, semiconductor patterns that extend from the semiconductor substrate and intersect one-side walls of the conductive patterns, charge storage layers interposed between the semiconductor patterns and one-side walls of the conductive patterns, and seed layer patterns interposed between the charge storage layers and one-side walls of the conductive patterns.

摘要翻译： 提供具有三维结构的非易失性存储器件及其制造方法。 非易失性存储器件包括三维地布置在半导体衬底上的导电图案，半导体图案从半导体衬底延伸并与导电图案的一侧壁相交，插入在半导体图案和半导体图案的一侧壁之间的电荷存储层 导电图案和介于电荷存储层和导电图案的单侧壁之间的种子层图案。

公开(公告)号：US20120003831A1

公开(公告)日：2012-01-05

申请号：US13173591

申请日：2011-06-30

申请人： Daehyuk Kang ,  Sang Won Bae ,  Boun Yoon ,  Kuntach Lee ,  Young-Hoo Kim

发明人： Daehyuk Kang ,  Sang Won Bae ,  Boun Yoon ,  Kuntach Lee ,  Young-Hoo Kim

IPC分类号： H01L21/8239

CPC分类号： H01L27/11578 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

摘要： Methods of forming nonvolatile memory devices include forming a stack of layers of different materials on a substrate. This stack includes a plurality of first layers of a first material and a plurality of second layers of a second material arranged in an alternating sequence of first and second layers. A selected first portion of the stack of layers is isotropically etched for a sufficient duration to define a first trench therein that exposes sidewalls of the alternating sequence of first and second layers. The sidewalls of each of the plurality of first layers are selectively etched relative to sidewalls of adjacent ones of the plurality of second layers. Another etching step is then performed to recess sidewalls of the plurality of second layers and thereby expose portions of upper surfaces of the plurality of first layers. These exposed portions of the upper surfaces of the plurality of first layers, which may act as word lines of a memory device, are displaced laterally relative to each other.

摘要翻译： 形成非易失性存储器件的方法包括在衬底上形成不同材料层的堆叠。 该堆叠包括以第一和第二层的交替顺序布置的多个第一材料的第一层和多个第二层的第二层。 各层的所选择的第一部分被各向同性蚀刻足够的持续时间以限定其中的第一沟槽的第一和第二层的交替序列的侧壁。 多个第一层中的每一个的侧壁相对于多个第二层中的相邻侧壁的侧壁被选择性地蚀刻。 然后执行另一蚀刻步骤以使多个第二层的侧壁凹陷，从而暴露多个第一层的上表面的部分。 可以充当存储器件的字线的多个第一层的上表面的这些暴露部分相对于彼此横向偏移。

公开(公告)号：US20100200431A1

公开(公告)日：2010-08-12

申请号：US12704206

申请日：2010-02-11

申请人： Youngok Kim ,  Jeongnam Han ,  Changki Hong ,  Boun Yoon ,  Kuntack Lee ,  Young-Hoo Kim

发明人： Youngok Kim ,  Jeongnam Han ,  Changki Hong ,  Boun Yoon ,  Kuntack Lee ,  Young-Hoo Kim

IPC分类号： G01N27/26

CPC分类号： H01L22/14

摘要： The inventive concept provides a wafer test method and a wafer test apparatus. The wafer test method can recognize the amount of residuals generated in a sidewall of the metal-containing layer pattern and the extent of corrosion of a sidewall of the metal-containing layer pattern using the measured electric resistance by supplying an electrolyte so that the electrolyte is in contact with a portion of the metal-containing layer pattern in a predetermined chip region and measuring an electric resistance between a first electrode which is electrically in contact with the other portion of the metal-containing layer pattern and a second electrode which is in contact with the electrolyte in the predetermined region. Thus, a wafer test method and a wafer test apparatus can be embodied by an in-line method without dividing a wafer into each chip.

摘要翻译： 本发明的概念提供了晶片测试方法和晶片测试装置。 晶片测试方法可以通过提供电解质来确定含金属层图案的侧壁中产生的残留量以及含金属层图案的侧壁的腐蚀程度，使得电解质为 与预定芯片区域中的含金属层图案的一部分接触，并且测量与含金属层图案的另一部分电接触的第一电极和接触的第二电极之间的电阻 电解液在预定区域内。 因此，可以通过在线方式来实现晶片测试方法和晶片测试装置，而不将晶片分成每个芯片。

公开(公告)号：US08228089B2

公开(公告)日：2012-07-24

申请号：US12704206

申请日：2010-02-11

申请人： Youngok Kim ,  Jeongnam Han ,  Changki Hong ,  Boun Yoon ,  Kuntack Lee ,  Young-Hoo Kim

发明人： Youngok Kim ,  Jeongnam Han ,  Changki Hong ,  Boun Yoon ,  Kuntack Lee ,  Young-Hoo Kim

IPC分类号： G01R31/26 ,  G01R31/08 ,  H01L21/66

CPC分类号： H01L22/14

摘要： The inventive concept provides a wafer test method and a wafer test apparatus. The wafer test method can recognize the amount of residuals generated in a sidewall of the metal-containing layer pattern and the extent of corrosion of a sidewall of the metal-containing layer pattern using the measured electric resistance by supplying an electrolyte so that the electrolyte is in contact with a portion of the metal-containing layer pattern in a predetermined chip region and measuring an electric resistance between a first electrode which is electrically in contact with the other portion of the metal-containing layer pattern and a second electrode which is in contact with the electrolyte in the predetermined region. Thus, a wafer test method and a wafer test apparatus can be embodied by an in-line method without dividing a wafer into each chip.

摘要翻译： 本发明的概念提供了晶片测试方法和晶片测试装置。 晶片测试方法可以通过提供电解质来确定含金属层图案的侧壁中产生的残留量以及含金属层图案的侧壁的腐蚀程度，使得电解质为 与预定芯片区域中的含金属层图案的一部分接触，并且测量与含金属层图案的另一部分电接触的第一电极和接触的第二电极之间的电阻 电解液在预定区域内。 因此，可以通过在线方式来实现晶片测试方法和晶片测试装置，而不将晶片分成每个芯片。

公开(公告)号：US10128336B2

公开(公告)日：2018-11-13

申请号：US15009119

申请日：2016-01-28

申请人： Sangjine Park ,  Boun Yoon ,  Jeongnam Han

发明人： Sangjine Park ,  Boun Yoon ,  Jeongnam Han

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/78 ,  H01L23/535 ,  H01L29/16 ,  H01L29/165 ,  H01L29/45 ,  H01L29/417

摘要： Semiconductor devices and methods of manufacturing semiconductor devices. A semiconductor device includes a metal gate electrode stacked on a semiconductor substrate with a gate insulation layer disposed therebetween, spacer structures disposed on the semiconductor substrate at both sides of the metal gate electrode, source/drain regions formed in the semiconductor substrate at the both sides of the metal gate electrode, and an etch stop pattern including a bottom portion covering the source/drain regions and a sidewall portion extended from the bottom portion to cover a portion of sidewalls of the spacer structures, in which an upper surface of the sidewall portion of the etch stop pattern is positioned under an upper surface of the metal gate electrode.

公开(公告)号：US09748234B2

公开(公告)日：2017-08-29

申请号：US14826811

申请日：2015-08-14

申请人： Kee Sang Kwon ,  Boun Yoon ,  Sangjine Park ,  Myunggeun Song ,  Ki-Hyung Ko ,  Jiwon Yun

发明人： Kee Sang Kwon ,  Boun Yoon ,  Sangjine Park ,  Myunggeun Song ,  Ki-Hyung Ko ,  Jiwon Yun

IPC分类号： H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L27/0886 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/785

摘要： Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of the gate electrodes may include a gate insulating pattern on the substrate, a lower work-function electrode pattern that is on the gate insulating pattern and has a recessed upper surface, and an upper work-function electrode pattern that conformally extends on the recessed upper surface of the lower work-function electrode pattern. Topmost surfaces of the lower work-function electrode patterns may be disposed at an equal level, and the upper work-function electrode patterns may have different thicknesses from each other.

公开(公告)号：US08946026B2

公开(公告)日：2015-02-03

申请号：US13238284

申请日：2011-09-21

申请人： Sukhun Choi ,  Boun Yoon ,  Jae-Jik Baek ,  Byung-Kwon Cho

发明人： Sukhun Choi ,  Boun Yoon ,  Jae-Jik Baek ,  Byung-Kwon Cho

IPC分类号： H01L21/8238 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/32139 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

摘要： A method of fabricating semiconductor devices having metal gate electrodes includes forming an insulating layer on a semiconductor substrate having a first region and a second region. The insulating layer is formed to include an interlayer insulating layer and a gate insulation layer. The interlayer insulating layer has first and second grooves respectively disposed in the first and second regions, and the gate insulation layer covers at least bottom surfaces of the first and second grooves. A laminated metal layer is formed on the substrate having the insulating layer. A planarization layer having non-photo sensitivity is formed on the laminated metal layer. The planarization layer in the first region is selectively removed using a dry etching process to expose the laminated metal layer in the first region and to form a planarization layer pattern covering the laminated metal layer in the second region.

摘要翻译： 制造具有金属栅电极的半导体器件的方法包括在具有第一区域和第二区域的半导体衬底上形成绝缘层。 绝缘层形成为包括层间绝缘层和栅极绝缘层。 层间绝缘层具有分别设置在第一和第二区域中的第一和第二沟槽，并且栅极绝缘层至少覆盖第一和第二沟槽的至少底表面。 在具有绝缘层的基板上形成层叠金属层。 在层叠金属层上形成具有非光敏性的平坦化层。 使用干蚀刻工艺选择性地去除第一区域中的平坦化层，以暴露第一区域中的层压金属层，并形成覆盖第二区域中的层叠金属层的平坦化图案。