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    DELAY LOCKED LOOP
    2.
    发明申请
    DELAY LOCKED LOOP 有权
    延迟锁定环

    公开(公告)号：US20100283520A1

    公开(公告)日：2010-11-11

    申请号：US12840643

    申请日：2010-07-21

    申请人： Young-Jun Ku

    发明人： Young-Jun Ku

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03L7/10

    摘要： A semiconductor memory device includes a delay locked loop for achieving a delay locked state by correcting a phase difference between a reference clock and an internal delayed clock and for indicating the state that a larger delay amount than a maximum delay amount of a delay line is required, or a smaller delay amount than a minimum delay amount of delay line is required. A control unit resets the delay locked loop according to the state of the delay line.

    摘要翻译： 半导体存储器件包括延迟锁定环路，用于通过校正参考时钟和内部延迟时钟之间的相位差来实现延迟锁定状态，并且用于指示需要比延迟线的最大延迟量更大的延迟量的状态 或者需要比延迟线的最小延迟量小的延迟量。 控制单元根据延迟线的状态复位延迟锁定环。

    Delay locked loop and semiconductor memory device with the same
    3.
    发明申请
    Delay locked loop and semiconductor memory device with the same 失效
    延迟锁定环和半导体存储器件相同

    公开(公告)号：US20080239846A1

    公开(公告)日：2008-10-02

    申请号：US12003552

    申请日：2007-12-28

    申请人： Young-Jun Ku

    发明人： Young-Jun Ku

    IPC分类号： G11C7/12 ,  G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/12 ,  G11C7/20 ,  G11C7/222

    摘要： A semiconductor memory device is capable of controlling a delay locked loop appropriately based on operation modes, particularly in a fast power-down mode to reduce an amount of current maximumly. The semiconductor memory device includes a delay-locked clock signal generating unit, a mode signal generating unit, and a delay locking control unit. The delay-locked clock signal generating unit performs a delay locking operation on a clock signal, thereby generating a delay-locked clock signal. The mode signal generating unit enables a fast precharge power-down mode signal in a fast precharge power-down mode. The delay locking control unit controls the delay-locked clock signal generating unit to be activated in a predetermined cycle in response to the fast precharge power-down mode signal.

    摘要翻译： 半导体存储器件能够基于操作模式适当地控制延迟锁定环路，特别是在快速掉电模式下最大程度地减少电流量。 半导体存储器件包括延迟锁定时钟信号产生单元，模式信号产生单元和延迟锁定控制单元。 延迟锁定时钟信号产生单元对时钟信号执行延迟锁定操作，从而产生延迟锁定时钟信号。 模式信号产生单元在快速预充电掉电模式下启用快速预充电掉电模式信号。 延迟锁定控制单元响应于快速预充电掉电模式信号控制延迟锁定时钟信号产生单元在预定周期中被激活。

    Apparatus for generating internal voltage
    4.
    发明申请
    Apparatus for generating internal voltage 有权
    用于产生内部电压的装置

    公开(公告)号：US20060232302A1

    公开(公告)日：2006-10-19

    申请号：US11321115

    申请日：2005-12-28

    申请人： Kang-Seol Lee ,  Young-Jun Ku

    发明人： Kang-Seol Lee ,  Young-Jun Ku

    IPC分类号： G01N30/86

    CPC分类号： G11C5/147 ,  G05F1/465

    摘要： An internal voltage generator according to the present invention stably supplies an internal voltage regardless a level of power voltage input from a source external to a semiconductor memory device. The present invention includes a dead zone controller to generate a reference voltage, a high reference voltage and a low reference voltage based on an inputted power voltage; and an internal power generator to generate an internal power based on the reference voltage by comparing the internal power with the high reference voltage and the low reference voltage.

    摘要翻译： 根据本发明的内部电压发生器，与从半导体存储器件外部的源极输入的电源电压的电平无关地稳定地提供内部电压。 本发明包括基于输入的电源电压产生参考电压，高参考电压和低参考电压的死区控制器; 以及内部功率发生器，通过将内部功率与高参考电压和低参考电压进行比较，基于参考电压产生内部功率。

    Duty cycle corrector and clock generator having the same
    5.
    发明授权
    Duty cycle corrector and clock generator having the same 失效
    占空比校正器和时钟发生器具有相同的功能

    公开(公告)号：US07994834B2

    公开(公告)日：2011-08-09

    申请号：US12346005

    申请日：2008-12-30

    申请人： Young-Jun Ku

    发明人： Young-Jun Ku

    IPC分类号： H03K3/017 ,  H03K5/04 ,  H03K7/08

    CPC分类号： H03K3/017

    摘要： A duty cycle corrector includes a delay unit configured to adjust an input clock and an inverted input clock with a delay value controlled in response to one or more control signals and to generate a positive clock and a negative clock, and a duty detector configured to receive the positive clock and the negative clock, to detect duty ratios of the positive clock and the negative clock and to generate the one or more control signals.

    摘要翻译： 占空比校正器包括：延迟单元，被配置为响应于一个或多个控制信号调整输入时钟和反相输入时钟，延迟值被控制，并产生正时钟和负时钟，以及占空比检测器，被配置为接收 正时钟和负时钟，以检测正时钟和负时钟的占空比，并产生一个或多个控制信号。

    DATA INPUT DEVICE OF SEMICONDUCTOR MEMORY APPARTUS AND CONTROL METHOD THEREOF
    6.
    发明申请
    DATA INPUT DEVICE OF SEMICONDUCTOR MEMORY APPARTUS AND CONTROL METHOD THEREOF 有权
    半导体存储器的数据输入装置及其控制方法

    公开(公告)号：US20100165750A1

    公开(公告)日：2010-07-01

    申请号：US12490859

    申请日：2009-06-24

    申请人： Ki-Ho Kim ,  Young-Jun Ku

    发明人： Ki-Ho Kim ,  Young-Jun Ku

    IPC分类号： G11C7/10 ,  G11C7/00 ,  G11C7/02

    CPC分类号： G11C7/1078 ,  G11C7/1084 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4093

    摘要： A data input device of a semiconductor memory apparatus includes input means configured to input data; precharge means configured to supply a precharge voltage for converting inputted data to a differential signal; enable means configured to enable the input means and the precharge means to operate; and control means configured to control a current amount of the enable means in a standby mode.

    摘要翻译： 半导体存储装置的数据输入装置包括被配置为输入数据的输入装置; 预充电装置，被配置为提供用于将输入的数据转换成差分信号的预充电电压; 启用装置，被配置为使得所述输入装置和所述预充电装置能够操作; 以及控制装置，被配置为在待机模式下控制使能装置的当前量。

    REGISTER CONTROLLED DELAY LOCKED LOOP CIRCUIT
    7.
    发明申请
    REGISTER CONTROLLED DELAY LOCKED LOOP CIRCUIT 失效
    寄存器控制延迟锁定环路

    公开(公告)号：US20090256604A1

    公开(公告)日：2009-10-15

    申请号：US12337562

    申请日：2008-12-17

    申请人： Young-Jun Ku

    发明人： Young-Jun Ku

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03L7/0818

    摘要： A register controlled DLL circuit occupies a relatively small area in a semiconductor device by reducing the number of flip-flops for generating timing pulses that are used to control a DLL operation and sequentially toggled. The registered controlled DLL circuit for generating a DLL clock by delaying internal clocks includes a timing pre-pulse generating unit configured to generate a plurality of timing pre-pulses activated sequentially in response to a source clock, the plurality of pre-pulses being repeated two or more times in each delay shifting update period, a mask signal generating unit configured to generating a mask signal having a logic level varied according to toggling of a predetermined one of the timing pre-pulses, and a timing pulse outputting unit configured to output the plurality of timing pre-pulses as a plurality of timing pulses in response to the mask signal.

    摘要翻译： 寄存器控制DLL电路通过减少用于产生用于控制DLL操作并顺序切换的定时脉冲的触发器的数量，在半导体器件中占据相对较小的面积。 用于通过延迟内部时钟产生DLL时钟的注册控制DLL电路包括：定时预脉冲生成单元，被配置为产生响应源时钟顺序激活的多个定时预脉冲，多个预脉冲重复两次 在每个延迟移位更新周期中多个时间，掩模信号产生单元，其被配置为产生具有根据预定的一个定时预脉冲的切换而变化的逻辑电平的屏蔽信号;以及定时脉冲输出单元， 多个定时预脉冲作为响应于掩模信号的多个定时脉冲。

    Semiconductor memory device capable of effectively testing failure of data
    8.
    发明授权
    Semiconductor memory device capable of effectively testing failure of data 有权
    能够有效测试数据故障的半导体存储器件

    公开(公告)号：US07492653B2

    公开(公告)日：2009-02-17

    申请号：US11647633

    申请日：2006-12-28

    申请人： Young-Jun Ku ,  Beom-Ju Shin

    发明人： Young-Jun Ku ,  Beom-Ju Shin

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C29/02 ,  G11C7/1039 ,  G11C29/022 ,  G11C29/025

    摘要： The present invention relates to an apparatus and a method for detecting a failure of data in the semiconductor memory device. The semiconductor memory device according to the present invention includes: a global I/O line for transferring data between an external circuit and a local I/O line; an I/O sense amplifier for controlling a data transmission between the local I/O line and the global I/O line; and an I/O sense amplifier control unit for controlling the I/O sense amplifier in response to a test mode signal in order to test the semiconductor memory device, independent of the data outputted from a memory cell.

    摘要翻译： 本发明涉及一种用于检测半导体存储器件中的数据故障的装置和方法。 根据本发明的半导体存储器件包括：用于在外部电路和本地I / O线之间传送数据的全局I / O线; 用于控制本地I / O线和全局I / O线之间的数据传输的I / O读出放大器; 以及I / O读出放大器控制单元，用于响应于测试模式信号控制I / O读出放大器，以便与存储单元输出的数据无关地测试半导体存储器件。

    Delay locked loop in synchronous semiconductor memory device and driving method thereof
    9.
    发明授权
    Delay locked loop in synchronous semiconductor memory device and driving method thereof 有权
    同步半导体存储器件中的延迟锁定环及其驱动方法

    公开(公告)号：US07489170B2

    公开(公告)日：2009-02-10

    申请号：US11528644

    申请日：2006-09-28

    申请人： Young-Jun Ku ,  Seok-Cheol Yoon

    发明人： Young-Jun Ku ,  Seok-Cheol Yoon

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0812 ,  G11C7/1072 ,  G11C7/222 ,  H03L7/0805

    摘要： A semiconductor memory device including a delay locked loop can minimize current consumption during a precharge power down mode. The delay locked loop includes a buffer control block for generating a clock buffer enable signal in response to first and second signals, wherein the first signal represents a precharge power down mode and the second signal represents a reset of the delay locked loop, a clock buffering block, controlled by the clock buffer enable signal, for buffering an external clock to generate a reference clock, and a feedback loop for delaying the reference clock until a delay locking state to thereby output a DLL output clock.

    摘要翻译： 包括延迟锁定环路的半导体存储器件可以使预充电掉电模式期间的电流消耗最小化。 延迟锁定环包括缓冲器控制块，用于响应于第一和第二信号产生时钟缓冲器使能信号，其中第一信号表示预充电掉电模式，第二信号表示延迟锁定环的复位，时钟缓冲 由时钟缓冲器使能信号控制，用于缓冲外部时钟以产生参考时钟，以及用于延迟参考时钟直到延迟锁定状态从而输出DLL输出时钟的反馈回路。

    Semiconductor memory device and method for driving the same
    10.
    发明申请
    Semiconductor memory device and method for driving the same 有权
    半导体存储器件及其驱动方法

    公开(公告)号：US20080165607A1

    公开(公告)日：2008-07-10

    申请号：US11824359

    申请日：2007-06-29

    申请人： Kyoung-Nam Kim ,  Young-Jun Ku ,  Hoon Choi

    发明人： Kyoung-Nam Kim ,  Young-Jun Ku ,  Hoon Choi

    IPC分类号： G11C5/14

    CPC分类号： G11C7/22 ,  G11C7/222

    摘要： A semiconductor memory device includes: a delay locked loop (DLL) clock buffer for buffering a system clock in response to the a buffer enable signal; a DLL circuit for generating a delay locked loop (DLL) clock by performing a delay locking operation using the buffered system clock; and a DLL clock buffer controller for generating the buffer enable signal in response to a code signal and a clock enable signal, the code signal containing information about whether to perform the delay locking operation.

    摘要翻译： 半导体存储器件包括：响应于缓冲器使能信号缓冲系统时钟的延迟锁定环（DLL）时钟缓冲器; 一个DLL电路，用于通过使用缓冲的系统时钟执行延迟锁定操作来产生延迟锁定环（DLL）时钟; 以及DLL时钟缓冲器控制器，用于响应于代码信号和时钟使能信号产生缓冲器使能信号，所述代码信号包含关于是否执行延迟锁定操作的信息。