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    ACTIVATION SYSTEM FOR ELECTRONIC URINAL
    1.
    发明申请
    ACTIVATION SYSTEM FOR ELECTRONIC URINAL 审中-公开

    公开(公告)号：US20180051451A1

    公开(公告)日：2018-02-22

    申请号：US15239910

    申请日：2016-08-18

    Applicant: Hsiang-Hung Wang ,  Yu-Chang Lin

    Inventor： Hsiang-Hung Wang ,  Yu-Chang Lin

    IPC: E03D5/10 ,  E03D13/00

    CPC classification number: E03D5/105 ,  E03D13/00

    Abstract: An activation system for electronic urinal comprises a urinal fluidly communicated with an inlet pipe and a control unit arranged between the urinal and the inlet pipe. The control unit includes a solenoid valve, a sensor, and a power supply. The solenoid valve is used for controlling to water or seal. The sensor is electrically connected to the solenoid valve. The power supply provides power to the solenoid valve and the sensor. The control unit has an activation switch which is electrically connected to the solenoid valve. The activation switch has a wireless transmission module and a timing controller for turning off the wireless transmission module. The activation switch is pressed so that the wireless transmission module is activated to set water discharge and a turn-off time of the solenoid valve and is turned off after a preset time counted by the time controller to save power.

    Standby current erasion circuit of DRAM
    3.
    发明授权
    Standby current erasion circuit of DRAM 有权
    DRAM的待机电流擦除电路

    公开(公告)号：US07652290B2

    公开(公告)日：2010-01-26

    申请号：US10232460

    申请日：2002-08-30

    Applicant: Yu-Chang Lin

    Inventor： Yu-Chang Lin

    IPC: H01L27/108 ,  G11C29/04 ,  G11C29/12 ,  G11C29/50 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14 ,  G11C7/12 ,  G11C7/18

    CPC classification number: G11C11/4085 ,  G11C2207/2227

    Abstract: The present invention discloses a standby current erasion circuit applied in DRAM, which improves prior art word line driving circuit to have the word line voltage outputted in standby mode be equal to the bit line voltage, thereby the short DC standby current between the word line and bit line can be erased.

    Abstract translation: 本发明公开了一种应用在DRAM中的待机电流擦除电路，其改进了现有技术的字线驱动电路，使待机模式下输出的字线电压等于位线电压，从而在字线和 位线可以被擦除。

    ESD protection scheme for semiconductor devices having dummy pads
    4.
    发明申请
    ESD protection scheme for semiconductor devices having dummy pads 审中-公开

    公开(公告)号：US20080174923A1

    公开(公告)日：2008-07-24

    申请号：US11812221

    申请日：2007-06-15

    Applicant: Yi-Hsun Wu ,  Yan-Chih Jiang ,  Yu-Chang Lin ,  Jian-Hsing Lee

    Inventor： Yi-Hsun Wu ,  Yan-Chih Jiang ,  Yu-Chang Lin ,  Jian-Hsing Lee

    IPC: H02H9/00 ,  H01L21/336

    CPC classification number: H01L27/0255

    Abstract: A semiconductor device formed in a semiconductor substrate for dissipating electrostatic discharge and/or accumulated charge in an integrated circuit is provided. In one embodiment, the device comprises a semiconductor substrate; a plurality of layers of metal lines formed overlying the substrate; a plurality of via plugs through intermetal dielectric layers between the layers of metal lines and wherein the via plugs interconnect the metal lines; and a dummy pad formed over the plurality of layers of metal lines, the dummy pad having a diode connected thereto and to ground for providing a discharge path for the electrostatic discharge and/or accumulated charge.

    Test key for monitoring gate conductor to deep trench misalignment
    5.
    发明授权
    Test key for monitoring gate conductor to deep trench misalignment 有权
    测试键用于监控栅极导体与深沟槽的未对准

    公开(公告)号：US07189586B2

    公开(公告)日：2007-03-13

    申请号：US10904652

    申请日：2004-11-21

    Applicant: Yu-Chang Lin

    Inventor： Yu-Chang Lin

    IPC: H01L21/66 ,  H01L23/58

    CPC classification number: H01L22/34 ,  Y10S257/905 ,  Y10S257/908

    Abstract: A test key for monitoring GC-DT misalignment is provided. Deep trench capacitors are embedded in an interlacing matrix manner. GC lines are defined on a substrate and passing over the deep trench capacitors. A first bit line contact pattern surrounded by first assistant bit line contact patterns is disposed on the right side of a first deep trench capacitor. A second bit line contact pattern surrounded by second assistant bit line contact patterns is disposed on the left side of a second deep trench capacitor. The test key has a mirror symmetric line. The first assistant bit line contact patterns and second assistant bit line contact patterns are symmetric with respect to the mirror symmetric line. An active area connects the first bit line contact pattern and the second bit line contact pattern. A signal-in bit line is connected to the first bit line contact and a signal-out bit line is connected to the second bit line contact. The rest rows of the bit lines are dummy bit lines and floating.

    Abstract translation: 提供了一个用于监测GC-DT不对准的测试键。 深沟槽电容器以隔行矩阵的方式嵌入。 GC线定义在衬底上并穿过深沟槽电容器。 由第一辅助位线接触图案包围的第一位线接触图案设置在第一深沟槽电容器的右侧。 由第二辅助位线接触图案包围的第二位线接触图案设置在第二深沟槽电容器的左侧。 测试键具有镜像对称线。 第一辅助位线接触图案和第二辅助位线接触图案相对于镜像对称线对称。 有源区域连接第一位线接触图案和第二位线接触图案。 信号输入位线连接到第一位线触点，并且信号输出位线连接到第二位线触点。 位线的其余行是虚拟位线和浮动。

    Method and apparatus for independentlyrefreshing memory capacitors
    7.
    发明申请
    Method and apparatus for independentlyrefreshing memory capacitors 有权
    独立储存电容器的方法和装置

    公开(公告)号：US20050035959A1

    公开(公告)日：2005-02-17

    申请号：US10707652

    申请日：2003-12-30

    Applicant: Yu-Chang Lin ,  Ying-Te Tu

    Inventor： Yu-Chang Lin ,  Ying-Te Tu

    IPC: G09G5/00 ,  G11C11/403 ,  G11C11/406

    CPC classification number: G11C11/406 ,  G11C2211/4065

    Abstract: A method for refreshing a memory capacitor is provided. First, the refresh controller provides a refresh control signal. The pre-decoded row address counter counts and outputs a regular pre-decoded row address in response to the refresh control signal. The regular pre-decoded row address is inputted to the pre-decoded row address re-driver to obtain a row address. The memory capacitor in response to the row address is refreshed.

    Abstract translation: 提供一种刷新存储电容器的方法。 首先，刷新控制器提供刷新控制信号。 预编码行地址计数器响应于刷新控制信号计数并输出常规预解码行地址。 常规预解码行地址被输入到预解码行地址重新驱动器以获得行地址。 响应于行地址的存储电容被刷新。

    Devices and methods for detecting current leakage between deep trench capacitors in DRAM devices
    8.
    发明授权
    Devices and methods for detecting current leakage between deep trench capacitors in DRAM devices 有权
    用于检测DRAM器件中深沟槽电容器之间的电流泄漏的装置和方法

    公开(公告)号：US07443171B2

    公开(公告)日：2008-10-28

    申请号：US11619313

    申请日：2007-01-03

    Applicant: Yu-Chang Lin

    Inventor： Yu-Chang Lin

    IPC: G01R31/08

    CPC classification number: H01L27/0207 ,  G11C11/401 ,  G11C29/006 ,  G11C29/50 ,  G11C2029/5006 ,  H01L22/34 ,  H01L27/10861

    Abstract: A test device for detecting current leakage between deep trench capacitors in DRAM devices. The test device is disposed in a scribe line region of a wafer. In the test device, a first trench capacitor pair has a first deep trench capacitor and a second deep trench capacitor connected in parallel. A first transistor has a first terminal electrically coupled to the first deep trench capacitor and a control terminal electrically coupled to a first word line. A second transistor has a first terminal electrically coupled to the second deep trench capacitor and a control terminal electrically coupled to a second word line. First and second bit lines are electrically coupled to the first and second transistors respectively. The first and second bit lines are separated and the first and second word lines are perpendicular to the bit line regions.

    Abstract translation: 一种用于检测DRAM器件中深沟槽电容器之间的电流泄漏的测试装置。 测试装置设置在晶片的划线区域中。 在测试装置中，第一沟槽电容器对具有并联连接的第一深沟槽电容器和第二深沟槽电容器。 第一晶体管具有电耦合到第一深沟槽电容器的第一端子和电耦合到第一字线的控制端子。 第二晶体管具有电耦合到第二深沟槽电容器的第一端子和电耦合到第二字线的控制端子。 第一和第二位线分别电耦合到第一和第二晶体管。 第一和第二位线被分离，第一和第二字线垂直于位线区域。

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