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    3D GLASS, 3D IMAGE PROCESSING METHOD, COMPUTER READABLE STORAGE MEDIA CAN PERFORM THE 3D IMAGE PROCESSING METHOD
    1.
    发明申请
    3D GLASS, 3D IMAGE PROCESSING METHOD, COMPUTER READABLE STORAGE MEDIA CAN PERFORM THE 3D IMAGE PROCESSING METHOD 审中-公开
    3D玻璃，3D图像处理方法，计算机可读存储介质可执行3D图像处理方法

    公开(公告)号：US20120242650A1

    公开(公告)日：2012-09-27

    申请号：US13070490

    申请日：2011-03-24

    申请人： Yu-Yeh Chen ,  Jia-Jio Huang ,  Jhen-Wei He ,  Heng-Shun Kuan ,  Tsung-Hsien Lin

    发明人： Yu-Yeh Chen ,  Jia-Jio Huang ,  Jhen-Wei He ,  Heng-Shun Kuan ,  Tsung-Hsien Lin

    IPC分类号： G06T15/00

    CPC分类号： H04N13/373 ,  H04N13/122 ,  H04N13/341

    摘要： A 3D image processing method, for processing a dynamic image region swapping between a first dynamic image gray level and a second dynamic image gray level, comprising: determining a max dynamic gray level reference value and a min dynamic gray level reference value, to generate an adjusted dynamic gray level and luminance curve; generating a dynamic table, which includes relations between the adjusted dynamic gray level and luminance curve, the first and second dynamic image gray level, according to the adjusted gray level and luminance curve; and adjusting the first and second dynamic image gray level according to the dynamic table.

    摘要翻译： 一种3D图像处理方法，用于处理在第一动态图像灰度级和第二动态图像灰度级之间交换的动态图像区域，包括：确定最大动态灰度级参考值和最小动态灰度级参考值，以产生 调整动态灰度级和亮度曲线; 生成动态表，其中包括调整后的动态灰度级和亮度曲线之间的关系，第一和第二动态图像灰度级，根据调整的灰度级和亮度曲线; 并根据动态表调整第一和第二动态图像灰度级。

    Backlight module
    2.
    发明授权
    Backlight module 有权
    背光模组

    公开(公告)号：US08348444B2

    公开(公告)日：2013-01-08

    申请号：US12793692

    申请日：2010-06-04

    申请人： Kuang-Yu Fan ,  Cheng-Chuan Chen ,  Tsung-Hsien Lin ,  Shih-Jun Yuan

    发明人： Kuang-Yu Fan ,  Cheng-Chuan Chen ,  Tsung-Hsien Lin ,  Shih-Jun Yuan

    IPC分类号： G09F13/04

    摘要： A backlight module includes a back plate, a plurality of lamps, a lamp fixing base, and a diffusion plate. The back plate has a cavity. The lamps are disposed on or above the back plate. The lamp fixing base is disposed on the back plate for fixing the lamps. The lamp fixing base has a supporting portion extending along a direction away from the back plate. An orthogonal projection of the supporting portion on the back plate is within a boundary of the cavity. The diffusion plate is disposed above or over the back plate, and the supporting portion is suitable for supporting the diffusion plate.

    摘要翻译： 背光模块包括背板，多个灯，灯固定底座和扩散板。 背板有一个空腔。 灯设置在背板上或上面。 灯固定座设置在背板上用于固定灯。 灯固定座具有沿远离背板的方向延伸的支撑部。 背板上的支撑部分的正交突起在空腔的边界内。 扩散板设置在背板的上方或上方，支撑部适合于支撑扩散板。

    High speed differential signaling logic gate and applications thereof
    4.
    再颁专利
    High speed differential signaling logic gate and applications thereof 有权
    高速差分信号逻辑门及其应用

    公开(公告)号：USRE43160E1

    公开(公告)日：2012-02-07

    申请号：US12026164

    申请日：2008-02-05

    申请人： Tsung-Hsien Lin

    发明人： Tsung-Hsien Lin

    IPC分类号： H03K19/20

    CPC分类号： H03K19/09432

    摘要： A high-speed differential signaling logic gate includes a 1st input transistor, 2nd input transistor, complimentary transistor, current source, a 1st load, and a 2nd load. The 1st input transistor is operably coupled to receive a 1st input logic signal, which may be one phase of a first differential input signal. The 2nd input transistor is coupled in parallel with the 1st input transistor and is further coupled to receive a 2nd input logic signal, which may be one phase of a 2nd differential input signal. The complimentary transistor is operably coupled to the sources of the 1st and 2nd input transistors and to receive a complimentary input signal, which mimics the other phase of the 1st differential logic signal and the 2nd differential logic signal. The current source sinks a fixed current from the 1st and 2nd input transistors and the complimentary transistor. The 1st load is operably coupled to the drains of the 1st and 2nd input transistors to provide a 1st phase of a differential logic output. The 2nd load is coupled to the drain of the complimentary transistor to provide a 2nd phase of the differential logic output.

    摘要翻译： 高速差分信号逻辑门包括第一输入晶体管，第二输入晶体管，互补晶体管，电流源，第一负载和第二负载。 第一输入晶体管可操作地耦合以接收第一输入逻辑信号，其可以是第一差分输入信号的一相。 第二输入晶体管与第一输入晶体管并联并且进一步耦合以接收第二输入逻辑信号，其可以是第二差分输入信号的一相。 互补晶体管可操作地耦合到第一和第二输入晶体管的源极并且接收互补输入信号，其模拟第一差分逻辑信号和第二差分逻辑信号的另一相位。 电流源从第一和第二输入晶体管和互补晶体管吸收固定电流。 第一负载可操作地耦合到第一和第二输入晶体管的漏极，以提供差分逻辑输出的第一相。 第二负载耦合到互补晶体管的漏极，以提供差分逻辑输出的第二相。

    VOLTAGE-TO-TIME CONVERTER, AND VOLTAGE-TO-DIGITAL CONVERTING DEVICE HAVING THE SAME
    6.
    发明申请
    VOLTAGE-TO-TIME CONVERTER, AND VOLTAGE-TO-DIGITAL CONVERTING DEVICE HAVING THE SAME 有权
    具有电压转换器和电压到数字转换器件

    公开(公告)号：US20100182186A1

    公开(公告)日：2010-07-22

    申请号：US12469749

    申请日：2009-05-21

    申请人： Tsung-Hsien Lin ,  Chung-Hsing Yang ,  Wei-Hao Chiu

    发明人： Tsung-Hsien Lin ,  Chung-Hsing Yang ,  Wei-Hao Chiu

    IPC分类号： H03M1/50

    CPC分类号： H03M1/50

    摘要： A voltage-to-digital converting device includes a first voltage-to-time converter outputting a first delay clock having a first time delay relative to a reference clock in response to an input voltage, and a second voltage-to-time converter outputting a second delay clock having a second time delay relative to the reference clock in response to a feedback voltage. The first and second time delays correspond respectively to the input and feedback voltages. A time-to-digital converting circuit receives the first and second delay clocks from the first and second voltage-to-time converters, compares phases of the first and second delay clocks, generates the feedback voltage based on result of phase comparison made thereby, and outputs a digital signal upon detecting that the phases of the first and second delay clocks are in-phase.

    摘要翻译： 电压 - 数字转换装置包括第一电压 - 时间转换器，其响应于输入电压输出相对于参考时钟具有第一时间延迟的第一延迟时钟;以及第二电压 - 时间转换器，其输出 第二延迟时钟响应于反馈电压具有相对于参考时钟的第二时间延迟。 第一和第二时间延迟分别对应于输入和反馈电压。 时间数字转换电路从第一和第二电压 - 时间转换器接收第一和第二延迟时钟，比较第一和第二延迟时钟的相位，基于由此产生的相位比较结果产生反馈电压， 并且在检测到第一和第二延迟时钟的相位是同相的时，输出数字信号。

    Method of fabricating thin film transistor and organic electro-luminescent display device
    7.
    发明授权
    Method of fabricating thin film transistor and organic electro-luminescent display device 有权
    制造薄膜晶体管和有机电致发光显示装置的方法

    公开(公告)号：US07741163B2

    公开(公告)日：2010-06-22

    申请号：US11309735

    申请日：2006-09-19

    申请人： Tarng-Shiang Hu ,  Yi-Kai Wang ,  Jing-Yi Yan ,  Tsung-Hsien Lin ,  Jia-Chong Ho

    发明人： Tarng-Shiang Hu ,  Yi-Kai Wang ,  Jing-Yi Yan ,  Tsung-Hsien Lin ,  Jia-Chong Ho

    IPC分类号： H01L21/00

    CPC分类号： H01L27/3262 ,  H01L51/524 ,  H01L51/5253 ,  H01L51/5259 ,  H01L2227/323 ,  Y10T428/24802

    摘要： A method of fabricating a thin film transistor is provided. A gate is formed on a substrate. A gate insulator is formed on the substrate to cover the gate. A source/drain layer is formed on the gate insulator, and a portion of the gate insulator above the gate is exposed by the source/drain layer. An isolated layer is formed on the source/drain layer and has an opening to expose a portion of the gate insulator and a portion of the source/drain layer above the gate. A channel layer is formed in the opening of the isolated layer to be electrically connected to the source/drain layer, and the channel layer is exposed by the opening.

    摘要翻译： 提供一种制造薄膜晶体管的方法。 栅极形成在基板上。 在基板上形成栅极绝缘体以覆盖栅极。 源极/漏极层形成在栅极绝缘体上，并且栅极上方的栅极绝缘体的一部分被源极/漏极层暴露。 在源极/漏极层上形成隔离层，并且具有用于暴露栅极绝缘体的一部分和栅极上方的源极/漏极层的一部分的开口。 沟道层形成在隔离层的开口中，以电连接到源极/漏极层，沟道层被开口暴露。

    METHOD OF FABRICATING ORGANIC SEMICONDUCTOR DEVICE
    8.
    发明申请
    METHOD OF FABRICATING ORGANIC SEMICONDUCTOR DEVICE 审中-公开
    制造有机半导体器件的方法

    公开(公告)号：US20090117686A1

    公开(公告)日：2009-05-07

    申请号：US12350931

    申请日：2009-01-08

    申请人： Liang-Ying Huang ,  Tsung-Hsien Lin ,  Hsiang-Yuan Cheng ,  Tarng-Shiang Hu

    发明人： Liang-Ying Huang ,  Tsung-Hsien Lin ,  Hsiang-Yuan Cheng ,  Tarng-Shiang Hu

    IPC分类号： H01L51/30

    CPC分类号： H01L51/0545 ,  H01L51/0018

    摘要： A method of fabricating an organic semiconductor device includes following steps. A gate conductive layer is formed on a substrate, and then a gate dielectric layer is formed. Next, patterned metal layers are formed on the gate dielectric layer beside the gate conductive layer. An electrode modified layer is then formed on the surface and the sidewall of each patterned metal layer, and the patterned metal layers and the electrode modified layers formed thereon serve as a source and a drain. Thereafter, an organic semiconductor layer is formed on the source and the drain and on a portion of the gate dielectric layer exposed between the source and the drain to be an active layer.

    摘要翻译： 制造有机半导体器件的方法包括以下步骤。 在基板上形成栅极导电层，然后形成栅极电介质层。 接下来，在栅极导电层旁边的栅极电介质层上形成图案化的金属层。 然后在每个图案化金属层的表面和侧壁上形成电极改性层，并且其上形成的图案化金属层和电极改性层用作源极和漏极。 此后，在源极和漏极以及暴露在源极和漏极之间的栅极电介质层的一部分上形成有机半导体层为有源层。

    Reflective liquid crystal display assembly
    9.
    发明申请
    Reflective liquid crystal display assembly 有权
    反光液晶显示组件

    公开(公告)号：US20070109471A1

    公开(公告)日：2007-05-17

    申请号：US11362203

    申请日：2006-02-27

    申请人： Chi-Lun Ting ,  Tsung-Hsien Lin ,  Chi-Chang Liao ,  Shie-Chang Jeng ,  Yan-Rung Lin ,  Ying-Guey Fuh

    发明人： Chi-Lun Ting ,  Tsung-Hsien Lin ,  Chi-Chang Liao ,  Shie-Chang Jeng ,  Yan-Rung Lin ,  Ying-Guey Fuh

    IPC分类号： G02F1/1335

    CPC分类号： G02F1/13718 ,  G02F1/1333 ,  G02F1/133707 ,  G02F2001/133368

    摘要： The present invention provides a reflective liquid crystal display assembly, which includes a first substrate, a second substrate and a liquid crystal layer sealed between them. The present invention designs a specific surface structure of at least one of the first and second substrates relative to the liquid crystal layer so that the helical axes of the cholesteric liquid crystal molecules can incline in different directions as desired in the liquid crystal layer. The reflective spectrum can be broadened and the viewing angle is widened.

    摘要翻译： 本发明提供一种反射型液晶显示组件，其包括第一基板，第二基板和密封在它们之间的液晶层。 本发明相对于液晶层设计第一和第二基板中的至少一个的比表面结构，使得胆甾醇型液晶分子的螺旋轴可以沿液晶层中所需的不同方向倾斜。 反射光谱可以变宽，视角扩大。

    Linearized fractional-N synthesizer having a gated offset
    10.
    发明申请
    Linearized fractional-N synthesizer having a gated offset 有权

    公开(公告)号：US20060035597A1

    公开(公告)日：2006-02-16

    申请号：US11222632

    申请日：2005-09-09

    申请人： Tsung-Hsien Lin ,  Hung-Ming Chien

    发明人： Tsung-Hsien Lin ,  Hung-Ming Chien

    IPC分类号： H04B1/40 ,  H04B7/00

    CPC分类号： H03L7/1976 ,  H03L7/0891 ,  H04W84/042 ,  H04W84/18 ,  H04W88/02

    摘要： A linearized oscillation synthesizer includes a phase and frequency detection module, charge pump circuit, low pass filter, voltage control oscillator, and a feedback module. The phase and frequency detection module is operably coupled to produce a charge-up signal, a charge-down signal, and an off signal based on phase and/or frequency differences between a reference oscillation and a feedback oscillation. The reference oscillation is generated by a clock source such as a crystal oscillator while the divider module generates the feedback oscillation by dividing the output oscillation by a divider value. The charge pump circuit produces a positive current in response to the charge-up signal, a negative current in response to the charge-down signal and also produces a non-zero offset current. The non-zero offset current shifts the steady state operating condition, and other operating conditions, of the charge pump into a linear region of charge pump performance curve.