公开(公告)号：US6100201A

公开(公告)日：2000-08-08

申请号：US33912

申请日：1998-03-03

申请人： Yukihiko Maejima ,  Jun Kawahara ,  Shinobu Saitoh ,  Yoshihiro Hayashi

发明人： Yukihiko Maejima ,  Jun Kawahara ,  Shinobu Saitoh ,  Yoshihiro Hayashi

IPC分类号： H01L21/8247 ,  H01L21/02 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792 ,  H01L21/461

CPC分类号： H01L28/55 ,  H01L21/3105 ,  H01L21/31122

摘要： A method of forming a capacitor by forming a dielectric layer over a bottom electrode layer, forming a top electrode layer over the dielectric layer to form laminations of the bottom electrode layer, the dielectric layer and the top electrode layer, and selectively etching the laminations to form a capacitor, the dielectric layer being etched by a reactive ion etching so that the dielectric layer of the capacitor receives no substantive damage in the etching process.

摘要翻译： 一种通过在底部电极层上形成电介质层形成电容器的方法，在电介质层上形成顶部电极层以形成底部电极层，电介质层和顶部电极层的叠层，并选择性地蚀刻叠片至 形成电容器，通过反应离子蚀刻蚀刻电介质层，使得电容器的电介质层在蚀刻工艺中不会受到实质的损坏。

公开(公告)号：US06709991B1

公开(公告)日：2004-03-23

申请号：US09084578

申请日：1998-05-26

申请人： Jun Kawahara ,  Shinobu Saito ,  Yukihiko Maejima ,  Yoshihiro Hayashi

发明人： Jun Kawahara ,  Shinobu Saito ,  Yukihiko Maejima ,  Yoshihiro Hayashi

IPC分类号： H01L21469

CPC分类号： H01L28/57 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02216 ,  H01L21/02219 ,  H01L21/02271 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76802

摘要： A fabrication method of a semiconductor device with a capacitor is provided, which prevents leakage current from increasing and dielectric breakdown resistance from decreasing during a CVD or dry etching process for forming an insulating film to cover the capacitor. In this method, a lower electrode of a capacitor is formed on a first insulating film. The first insulating film is typically formed on or over a semiconductor substrate. A dielectric film of the capacitor is formed on the lower electrode to be overlapped therewith. An upper electrode of the capacitor is formed on the dielectric film to be overlapped therewith. A second insulating film is formed to cover the capacitor by a thermal CVD process in an atmosphere containing no plasma at a substrate temperature in which hydrogen is prevented from being activated due to heat. A source material of the second insulating film has a property that no hydrogen is generated in the atmosphere through decomposition of the source material during the thermal CVD process.

摘要翻译： 提供了具有电容器的半导体器件的制造方法，其防止了在用于形成绝缘膜以覆盖电容器的CVD或干蚀刻工艺期间泄漏电流增加和绝缘击穿电阻降低。 在该方法中，在第一绝缘膜上形成电容器的下电极。 第一绝缘膜通常形成在半导体衬底上或上方。 电容器的电介质膜形成在下电极上以与其重叠。 电容器的上电极形成在电介质膜上以与其重叠。 形成第二绝缘膜，通过热CVD法在不防止由于热而被活化的基板温度下的不含等离子体的气氛中覆盖电容器。 第二绝缘膜的源材料具有通过在热CVD工艺期间源材料分解而在大气中不产生氢的性质。

公开(公告)号：US06295195B1

公开(公告)日：2001-09-25

申请号：US09472991

申请日：1999-12-28

申请人： Yukihiko Maejima

发明人： Yukihiko Maejima

IPC分类号： H01G400

CPC分类号： H01L28/55 ,  H01L21/76895 ,  H01L28/60

摘要： The present invention provides a method of patterning top and bottom electrodes of a capacitor. The method comprises the steps of: selectively forming a first mask made of a first material which has a barrier property to hydrogen on a top electrode of the capacitor; selectively etching a top electrode layer and a capacitive dielectric film by use of the first mask; without removing the first mask from the top electrode, selectively forming a second mask made of a second material which has a barrier property to hydrogen so that the second mask covers the first mask, the top electrode and the capacitive dielectric film and also covers a bottom electrode layer; and selectively etching a bottom electrode layer.

摘要翻译： 本发明提供一种图案化电容器的顶部和底部电极的方法。 该方法包括以下步骤：在电容器的顶部电极上选择性地形成由氢具有阻挡性的第一材料制成的第一掩模; 通过使用第一掩模选择性蚀刻顶部电极层和电容性电介质膜; 在不从顶部电极去除第一掩模的情况下，选择性地形成由具有对氢的阻挡性质的第二材料制成的第二掩模，使得第二掩模覆盖第一掩模，顶部电极和电容电介质膜，并且还覆盖底部 电极层; 并选择性地蚀刻底部电极层。

公开(公告)号：US06455327B1

公开(公告)日：2002-09-24

申请号：US09690492

申请日：2000-10-17

申请人： Yukihiko Maejima

发明人： Yukihiko Maejima

IPC分类号： H01G706

CPC分类号： H01L28/55 ,  H01L21/28568 ,  H01L28/75

摘要： In the manufacture of an integrated circuit memory capacitor, an underlying hydrogen barrier layer, either electrically nonconductive or conductive, is formed on a substrate. Then, the lower electrode layer and the ferroelectric/dielectric layer are formed and selectively etched. A nonconductive hydrogen barrier layer is formed on the dielectric layer and selectively etched. After a heat treatment in oxygen, the upper electrode layer and a conductive hydrogen barrier layer are successively deposited and selectively etched. The nonconductive hydrogen barrier layer covers the capacitor except for a part of the upper electrode, and the conductive hydrogen barrier layer covers a portion where there is no nonconductive hydrogen barrier layer. Thus, the underlying barrier layer, the nonconductive barrier layer and the conductive barrier layer together completely cover the memory capacitor. The dielectric layer comprises a ferroelectric or high-dielectric constant metal oxide. The nonconductive hydrogen barrier layer is typically SiN. The conductive hydrogen barrier layer is typically a metal nitride, such as TiN or AIN.

摘要翻译： 在集成电路存储器电容器的制造中，在衬底上形成导电或导电的潜在氢阻挡层。 然后，形成下电极层和铁电体/电介质层，并选择性地蚀刻。 在电介质层上形成非导电氢阻挡层并选择性地蚀刻。 在氧气中进行热处理后，依次沉积上电极层和导电氢阻挡层并选择性地蚀刻。 除了上部电极的一部分之外，不导电氢阻挡层覆盖电容器，并且导电氢阻挡层覆盖不存在非导电氢阻挡层的部分。 因此，下面的阻挡层，非导电阻挡层和导电阻挡层一起完全覆盖存储电容器。 电介质层包括铁电或高介电常数金属氧化物。 非导电氢阻挡层通常是SiN。 导电氢阻挡层通常是金属氮化物，例如TiN或AlN。

公开(公告)号：US06180971B2

公开(公告)日：2001-01-30

申请号：US09197919

申请日：1998-11-23

申请人： Yukihiko Maejima

发明人： Yukihiko Maejima

IPC分类号： H01L2976

CPC分类号： H01L28/55 ,  H01L21/28568 ,  H01L28/75

摘要： In the manufacture of an integrated circuit memory capacitor, an underlying hydrogen barrier layer, either electrically nonconductive or conductive, is formed on a substrate. Then, the lower electrode layer and the ferroelectric/dielectric layer are formed and selectively etched. A nonconductive hydrogen barrier layer is formed on the dielectric layer and selectively etched. After a heat treatment in oxygen, the upper electrode layer and a conductive hydrogen barrier layer are successively deposited and selectively etched. The nonconductive hydrogen barrier layer covers the capacitor except for a part of the upper electrode, and the conductive hydrogen barrier layer covers a portion where there is no nonconductive hydrogen barrier layer. Thus, the underlying barrier layer, the nonconductive barrier layer and the conductive barrier layer together completely cover the memory capacitor. The dielectric layer comprises a ferroelectric or high-dielectric constant metal oxide. The nonconductive hydrogen barrier layer is typically SiN. The conductive hydrogen barrier layer is typically a metal nitride, such as TiN or AlN.

摘要翻译： 在集成电路存储器电容器的制造中，在衬底上形成导电或导电的潜在氢阻挡层。 然后，形成下电极层和铁电体/电介质层，并选择性地蚀刻。 在电介质层上形成非导电氢阻挡层并选择性地蚀刻。 在氧气中进行热处理后，依次沉积上电极层和导电氢阻挡层并选择性地蚀刻。 除了上部电极的一部分之外，不导电氢阻挡层覆盖电容器，并且导电氢阻挡层覆盖不存在非导电氢阻挡层的部分。 因此，下面的阻挡层，非导电阻挡层和导电阻挡层一起完全覆盖存储电容器。 电介质层包括铁电或高介电常数金属氧化物。 非导电氢阻挡层通常是SiN。 导电氢阻挡层通常是金属氮化物，例如TiN或AlN。