摘要:
An embodiment is an integrated circuit. The integrated circuit comprises a clock generator and data transmission lines. The clock generator generates clock signals. At least some of the clock signals have a phase difference from an input clock signal input into the clock generator, and at least some of the clock signals have a different phase difference with respect to at least another of the clock signals. Each of the data transmission lines is triggered at least in part by at least one of the clock signals.
摘要:
A high-speed bus interface with an adaptive swing driver. A high speed interface includes a transmitter and a receiver coupled via a bus. The transmitter has an adaptive swing driver and a voltage-regulating-module (VRM). The adaptive swing driver includes a post-driver and a pre-driver. The post-driver provides an adaptive swing output with a dedicated adaptive voltage power supply (VDDQ) and transition emphasis driving capacity with an internal logic voltage supply (VDD). The pre-driver provides the transition emphasis driving capacity with a pull-up and a pull-down signal path to the post-driver. The voltage-regulating-module is configured to supply signal to the adaptive swing driver. The receiver includes a comparator and a bit-error-rate detector. The comparator amplifies the adaptive swing output received from the transmitter via a bus, while the bit-error-rate detector diagnoses the amplified adaptive swing output received from the comparator.
摘要:
An embodiment is an integrated circuit. The integrated circuit comprises a clock generator and data transmission lines. The clock generator generates clock signals. At least some of the clock signals have a phase difference from an input clock signal input into the clock generator, and at least some of the clock signals have a different phase difference with respect to at least another of the clock signals. Each of the data transmission lines is triggered at least in part by at least one of the clock signals.
摘要:
A method for signal phase calibration includes providing multiple periodic clock signals, including a reference signal and multiple phase shifted versions of the reference signal. The signals have a common frequency and are shifted from one another by multiples of a phase offset. An edge of a first signal is detected. The first signal is one of multiple phase shifted versions of the reference signal. The edge is a transition from a first logic value to a second logic value. The second logic value of the first signal is compared, upon detection of the edge, to a logic value of a second signal that is one of the first plurality of periodic clock signals other than the first signal. An inversion of the first signal is selectively provided based on an outcome of the comparison.
摘要:
A BIST circuit for high speed applications includes a phase difference detection circuit, a period-to-current conversion circuit having an input coupled to an output of the phase difference detection circuit and a current-to-voltage conversion circuit coupled to an output of the period-to-current conversion circuit. The phase difference detection circuit includes first NAND logic for receiving as inputs an input clock signal and a delayed version of an inverted version of the input clock signal; second NAND logic for receiving as inputs the inverted version of the input clock signal and a delayed version of the input clock signal; third NAND logic for receiving as inputs the input clock signal and the delayed version of the input clock signal; and fourth NAND logic for receiving as inputs the inverted version of the input clock signal and a delayed version of the inverted version of the input clock signal.
摘要:
The present disclosure relates to a clock generation system. The system includes a clock source, a tuning buffer, an output buffer, a duty cycle measurement circuit and an automatic calibration component. The clock source generates a clock signal. The tuning buffer is configured to generate a corrected clock signal from the clock signal according to adjustment values. The output buffer is configured to generate an output clock signal from the corrected clock signal. The duty cycle measurement circuit is configured measure a duty cycle of the output clock signal. The automatic calibration component is configured to generate the adjustment values according to the duty cycle measurement and the specification values.
摘要:
A voltage controlled oscillator (VCO) includes a current controlled oscillator, a voltage-to-current converter, and a sensing circuit. The sensing circuit includes a delay unit, and the sensing circuit is configured to generate a plurality of compensation control signals in response to a time delay of the delay unit. The voltage-to-current converter is configured to generate a current signal in response to a VCO control signal and the plurality of compensation control signals. The current controlled oscillator is configured to generate an oscillating signal in response to the current signal.
摘要:
The present disclosure relates to a clock generation system. The system includes a clock source, a tuning buffer, an output buffer, a duty cycle measurement circuit and an automatic calibration component. The clock source generates a clock signal. The tuning buffer is configured to generate a corrected clock signal from the clock signal according to adjustment values. The output buffer is configured to generate an output clock signal from the corrected clock signal. The duty cycle measurement circuit is configured measure a duty cycle of the output clock signal. The automatic calibration component is configured to generate the adjustment values according to the duty cycle measurement and the specification values.
摘要:
Some aspects of the present disclosure provide for a method of accurately simulating variations in an operating parameter, due to processing variations caused by a multi-patterning exposure, by reducing the impact of layout sections having a large width and spacing. The method assigns a skew sensitive index to one or more sections of a multi-patterning layer formed with a first mask. Runlengths of the one or more sections are respectively multiplied by an assigned skew sensitive index to determine a skew variation for each of the one or more sections. The overall skew variation sum is then determined by summing the skew variation for each of the one or more sections. By separately determining the effects of processing variations (e.g., mask misalignment) for different sections of a multi-patterning layer, an accurate measurement of operating parameter variations is achieved.
摘要:
A Phase Lock Loop (PLL) with gain control is provided. The PLL has a dual-path configuration, where a first and a second VCO control voltage are generated in response to a phase or frequency difference between a PLL input signal and an output signal. The PLL comprises a dynamic voltage gain control (DVGC) unit and a voltage-to-current (V2I) unit, where the DVGC creates a baseline reference current in response to the first VCO control voltage and the V2I provides a substantially linear current in response to the second VCO control voltage. The currents from the DVGC and V2I are combined and fed into a current-controlled oscillator, which generates a PLL output frequency signal. Frequency gain of the VCO is substantially reduced, thus providing a PLL with improved tuning precision.