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公开(公告)号:US20150287724A1
公开(公告)日:2015-10-08
申请号:US14746774
申请日:2015-06-22
IPC分类号: H01L27/092 , H01L23/00 , H01L23/532 , H01L27/02
CPC分类号: H01L23/49844 , H01L23/49811 , H01L23/50 , H01L23/5226 , H01L23/5286 , H01L23/53228 , H01L23/585 , H01L24/05 , H01L24/06 , H01L24/49 , H01L27/0255 , H01L27/092 , H01L2224/02166 , H01L2224/05025 , H01L2224/05093 , H01L2224/05095 , H01L2224/05124 , H01L2224/05624 , H01L2224/06102 , H01L2224/06133 , H01L2224/06143 , H01L2224/06153 , H01L2224/06163 , H01L2224/49105 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/12036 , H01L2924/1306 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
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公开(公告)号:US07714357B2
公开(公告)日:2010-05-11
申请号:US12253850
申请日:2008-10-17
CPC分类号: H01L23/49844 , H01L23/49811 , H01L23/50 , H01L23/5226 , H01L23/5286 , H01L23/53228 , H01L23/585 , H01L24/05 , H01L24/06 , H01L24/49 , H01L27/0255 , H01L27/092 , H01L2224/02166 , H01L2224/05025 , H01L2224/05093 , H01L2224/05095 , H01L2224/05124 , H01L2224/05624 , H01L2224/06102 , H01L2224/06133 , H01L2224/06143 , H01L2224/06153 , H01L2224/06163 , H01L2224/49105 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/12036 , H01L2924/1306 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
摘要翻译: 本发明的目的是提供一种能够减小半导体器件的平面尺寸的技术。 在半导体衬底上形成输入/输出电路,接地布线和电源布线通过输入/输出电路,并且在其上形成用于焊盘的导电层。 输入/输出电路由nMISFET形成区域和pMISFET形成区域中的MISFET元件形成,电阻元件形成区域中的电阻元件和用作保护元件的二极管元件形成区域中的二极管元件。 连接到保护元件并位于接地布线和电源布线下方的布线在nMISFET形成区域和pMISFET形成区域之间以及接地布线和要连接的电源布线之间的拉出区域中拉出 到导电层。
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公开(公告)号:US20170358564A1
公开(公告)日:2017-12-14
申请号:US15622394
申请日:2017-06-14
发明人: Tae-young Lee , Joon-young Oh , Sung-wook Hwang , Yeoung-jun Cho
CPC分类号: H01L25/18 , H01L23/3121 , H01L23/3128 , H01L24/16 , H01L24/32 , H01L24/33 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L25/0652 , H01L25/0657 , H01L2224/02381 , H01L2224/04042 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/49105 , H01L2224/49175 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/83191 , H01L2225/06506 , H01L2225/0651 , H01L2225/06517 , H01L2225/06527 , H01L2225/06562 , H01L2225/06575 , H01L2924/00014 , H01L2924/1431 , H01L2924/1436 , H01L2924/1438 , H01L2924/1461 , H01L2924/15311 , H01L2924/157 , H01L2924/15787 , H01L2924/1579 , H01L2924/181 , H01L2924/19107 , H01L2924/37001 , H01L2924/00012 , H01L2224/29099 , H01L2224/45099
摘要: A semiconductor package may be composed of a variety of different types of semiconductor chips of different sizes and support structures stacked within the semiconductor package. Semiconductor chips having a larger chip size may be stacked above smaller semiconductor chips. Smaller chips may be included in a layer of the semiconductor package along with a support structure which may assist supporting upper semiconductor chips, such as during a wire bonding process connecting bonding wires to chip pads of the semiconductor chips above the support structure. Use of different thicknesses of die attach film may allow for a further reduction in height of the semiconductor package. When implemented as a package housing a memory controller, DRAM semiconductor chips and non-volatile memory chips, locating the memory controller in a lower layer of the semiconductor package facilitates usage of the package substrate as a redistribution layer to provide communications between the memory controller and the DRAM and non-volatile memory chips.
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公开(公告)号:US20170317070A1
公开(公告)日:2017-11-02
申请号:US15142453
申请日:2016-04-29
IPC分类号: H01L27/02 , H04B1/40 , H01L23/532 , H01L23/552 , H01L23/00 , H01L25/18 , H01L27/06 , H01L29/06 , H01L29/73 , H01L23/495 , H01L23/528 , H01L23/522
CPC分类号: H01L27/0262 , H01L23/49541 , H01L23/5228 , H01L23/528 , H01L23/53271 , H01L23/552 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/18 , H01L27/0255 , H01L27/0647 , H01L29/0649 , H01L29/0684 , H01L29/0692 , H01L29/73 , H01L29/861 , H01L2224/32145 , H01L2224/48091 , H01L2224/48101 , H01L2224/48106 , H01L2224/48145 , H01L2224/48247 , H01L2224/49105 , H01L2224/49171 , H01L2224/73265 , H01L2924/1203 , H01L2924/12036 , H01L2924/1207 , H01L2924/13034 , H01L2924/1305 , H01L2924/13091 , H01L2924/1426 , H01L2924/3025 , H04B1/40 , H01L2924/00
摘要: An integrated circuit device for protecting circuits from transient electrical events is disclosed. An integrated circuit device includes a semiconductor substrate having formed therein a bidirectional semiconductor rectifier (SCR) having a cathode/anode electrically connected to a first terminal and an anode/cathode electrically connected to a second terminal. The integrated circuit device additionally includes a plurality of metallization levels formed above the semiconductor substrate. The integrated circuit device further includes a triggering device formed in the semiconductor substrate on a first side and adjacent to the bidirectional SCR. The triggering device includes one or more of a bipolar junction transistor (BJT) or an avalanche PN diode, where a first device terminal of the triggering device is commonly connected to the T1 with the K/A, and where a second device terminal of the triggering device is electrically connected to a central region of the bidirectional SCR through one or more of the metallization levels.
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公开(公告)号:US09515019B2
公开(公告)日:2016-12-06
申请号:US15099574
申请日:2016-04-14
IPC分类号: H01L29/74 , H01L23/50 , H01L23/498 , H01L27/092 , H01L27/02
CPC分类号: H01L23/49844 , H01L23/49811 , H01L23/50 , H01L23/5226 , H01L23/5286 , H01L23/53228 , H01L23/585 , H01L24/05 , H01L24/06 , H01L24/49 , H01L27/0255 , H01L27/092 , H01L2224/02166 , H01L2224/05025 , H01L2224/05093 , H01L2224/05095 , H01L2224/05124 , H01L2224/05624 , H01L2224/06102 , H01L2224/06133 , H01L2224/06143 , H01L2224/06153 , H01L2224/06163 , H01L2224/49105 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/12036 , H01L2924/1306 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
摘要翻译: 本发明的目的是提供一种能够减小半导体器件的平面尺寸的技术。 在半导体衬底上形成输入/输出电路,接地布线和电源布线通过输入/输出电路,并且在其上形成用于焊盘的导电层。 输入/输出电路由nMISFET形成区域和pMISFET形成区域中的MISFET元件形成,电阻元件形成区域中的电阻元件和用作保护元件的二极管元件形成区域中的二极管元件。 连接到保护元件并位于接地布线和电源布线下方的布线在nMISFET形成区域和pMISFET形成区域之间以及接地布线和要连接的电源布线之间的拉出区域中拉出 到导电层。
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公开(公告)号:US20140273344A1
公开(公告)日:2014-09-18
申请号:US13830041
申请日:2013-03-14
申请人: VISHAY-SILICONIX
发明人: Kyle TERRILL , Frank KUO , Sen MAO
IPC分类号: H01L23/00
CPC分类号: H01L25/074 , H01L21/4853 , H01L21/565 , H01L21/566 , H01L23/3107 , H01L23/3157 , H01L23/49513 , H01L23/49524 , H01L23/49541 , H01L23/49568 , H01L23/49575 , H01L23/49844 , H01L23/544 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L24/84 , H01L24/85 , H01L24/92 , H01L2223/54486 , H01L2224/27318 , H01L2224/2732 , H01L2224/291 , H01L2224/2929 , H01L2224/29294 , H01L2224/293 , H01L2224/32245 , H01L2224/33181 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/40499 , H01L2224/4103 , H01L2224/41051 , H01L2224/41052 , H01L2224/411 , H01L2224/41105 , H01L2224/4118 , H01L2224/48091 , H01L2224/48105 , H01L2224/48245 , H01L2224/48247 , H01L2224/49052 , H01L2224/49105 , H01L2224/73263 , H01L2224/73265 , H01L2224/73271 , H01L2224/83191 , H01L2224/83192 , H01L2224/83801 , H01L2224/83815 , H01L2224/8385 , H01L2224/83851 , H01L2224/8391 , H01L2224/84801 , H01L2224/84815 , H01L2224/8485 , H01L2224/8491 , H01L2224/9221 , H01L2224/92246 , H01L2224/92252 , H01L2924/00014 , H01L2924/00015 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2224/48 , H01L2924/014 , H01L2924/00012 , H01L2924/0665 , H01L2924/07811 , H01L2224/85 , H01L2224/45099 , H01L2224/05599
摘要: In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and a drain that are located on a first surface of the second die and the source that is located on a second surface of the second die that is opposite the first surface.
摘要翻译: 在一个实施例中,一种方法可以包括将第一管芯的栅极和源极耦合到引线框架。 第一管芯可以包括位于第一管芯的第一表面上的栅极和源极,以及位于第一管芯的与第一表面相对的第二表面上的漏极。 此外,该方法可以包括将第二管芯的源耦合到第一管芯的漏极。 第二管芯可以包括位于第二管芯的第一表面上的栅极和漏极,以及位于第二管芯的与第一表面相对的第二表面上的源极。
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公开(公告)号:US20090050940A1
公开(公告)日:2009-02-26
申请号:US12253850
申请日:2008-10-17
IPC分类号: H01L27/10
CPC分类号: H01L23/49844 , H01L23/49811 , H01L23/50 , H01L23/5226 , H01L23/5286 , H01L23/53228 , H01L23/585 , H01L24/05 , H01L24/06 , H01L24/49 , H01L27/0255 , H01L27/092 , H01L2224/02166 , H01L2224/05025 , H01L2224/05093 , H01L2224/05095 , H01L2224/05124 , H01L2224/05624 , H01L2224/06102 , H01L2224/06133 , H01L2224/06143 , H01L2224/06153 , H01L2224/06163 , H01L2224/49105 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/12036 , H01L2924/1306 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.
摘要翻译: 本发明的目的是提供一种能够减小半导体器件的平面尺寸的技术。 在半导体衬底上形成输入/输出电路,接地布线和电源布线通过输入/输出电路,并且在其上形成用于焊盘的导电层。 输入/输出电路由nMISFET形成区域和pMISFET形成区域中的MISFET元件形成,电阻元件形成区域中的电阻元件和用作保护元件的二极管元件形成区域中的二极管元件。 连接到保护元件并位于接地布线和电源布线下方的布线在nMISFET形成区域和pMISFET形成区域之间以及接地布线和要连接的电源布线之间的拉出区域中拉出 到导电层。
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公开(公告)号:US20190067539A1
公开(公告)日:2019-02-28
申请号:US15922578
申请日:2018-03-15
发明人: CHANG HOON KWAK , SUNG JIN AHN , HAK HWAN KIM , JIN HWAN KIM , JIN KWEON CHUNG , MIN JUNG KIM
IPC分类号: H01L33/62 , H01L33/50 , H01L33/36 , H01L23/29 , H01L23/488
CPC分类号: H01L33/62 , H01L23/293 , H01L23/488 , H01L33/36 , H01L33/382 , H01L33/50 , H01L33/501 , H01L33/505 , H01L33/54 , H01L33/56 , H01L2224/49105 , H01L2933/0033 , H01L2933/005 , H01L2933/0066
摘要: A semiconductor light-emitting diode (LED) package is provided and includes a semiconductor LED chip having a surface on which a first electrode and a second electrode are formed; a first solder bump formed on the first electrode and a second solder bump formed on the second electrode, the first solder bump and the second solder bump protruding from the surface of the semiconductor LED chip; and a resin layer having a bottom portion that surrounds a first side surface of the first solder bump and a second side surface of the second solder bump and covers the surface of the semiconductor LED chip.
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公开(公告)号:US20180005974A1
公开(公告)日:2018-01-04
申请号:US15619812
申请日:2017-06-12
发明人: Chin-Tien Chiu , Hem Takiar
IPC分类号: H01L23/00 , H01L25/065
CPC分类号: H01L24/49 , H01L24/17 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/05554 , H01L2224/49105 , H01L2224/49175 , H01L2225/06506 , H01L2225/0651 , H01L2225/06517 , H01L2225/06562 , H01L2225/06572 , H01L2225/06575 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/1438 , H01L2924/181 , H01L2924/37001 , H01L2224/45099 , H01L2924/00012
摘要: A semiconductor device is disclosed including at least first and second vertically stacked and interconnected semiconductor packages. Signal communication between the second semiconductor package and a host device occurs through the first semiconductor package.
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公开(公告)号:US20170317015A1
公开(公告)日:2017-11-02
申请号:US15484714
申请日:2017-04-11
发明人: Chia-Yen LEE , Hsin-Chang TSAI , Peng-Hsin LEE , Shiau-Shi LIN , Tzu-Hsuan CHENG
IPC分类号: H01L23/495 , H01L23/31 , H01L23/00 , H01L25/065 , H01L23/29
CPC分类号: H01L23/49586 , H01L23/29 , H01L23/3114 , H01L23/49575 , H01L24/09 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L2224/0233 , H01L2224/40245 , H01L2224/48137 , H01L2224/49105 , H01L2924/13064 , H01L2924/19105
摘要: A packaging structure is provided, including a substrate, a first chip, a second chip, and a conductive unit. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip by the conductive unit.
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