公开(公告)号：US07978043B2

公开(公告)日：2011-07-12

申请号：US12846451

申请日：2010-07-29

申请人： Yutaka Nabeshima ,  Yuichi Hirofuji

发明人： Yutaka Nabeshima ,  Yuichi Hirofuji

IPC分类号： H01F5/00

CPC分类号： H01L23/5227 ,  H01F17/0006 ,  H01F41/041 ,  H01F2017/0046 ,  H01L27/08 ,  H01L2924/0002 ,  H01Q1/2283 ,  H01Q7/00 ,  H01Q9/27 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate including at least one of a circuit and a circuit element, and an inductor element having a coil axis extending in a direction parallel to a main surface of the semiconductor substrate and disposed adjacent to the main surface. A main direction of a magnetic field induced by passing a current through the inductor element is parallel to the main surface.

摘要翻译： 半导体器件包括：半导体衬底，包括电路和电路元件中的至少一个;以及电感器元件，其具有沿与半导体衬底的主表面平行的方向延伸并且邻近主表面设置的线圈轴。 通过使电流通过电感器元件而引起的磁场的主要方向平行于主表面。

公开(公告)号：US5422013A

公开(公告)日：1995-06-06

申请号：US61074

申请日：1993-05-14

申请人： Yuichi Hirofuji

发明人： Yuichi Hirofuji

IPC分类号： C02F1/04 ,  C02F1/20 ,  C02F1/32 ,  C02F1/42 ,  C02F9/00 ,  C02F1/72 ,  B01D17/12

CPC分类号： C02F9/00 ,  C02F1/045 ,  C02F1/20 ,  C02F1/325 ,  C02F1/42 ,  C02F2201/3227 ,  Y10S210/90

摘要： A flow passage into which water-to-be-treated flows is provided with, in order from an upstream side, a deaerator as a DO eliminating device having a power variable mechanism, an oxidation device for oxidizing TOC by irradiating ultraviolet-ray, an ion eliminating device for eliminating TOC ion generated at oxidation, and a particle eliminating device. Further provided thereat are a TOC density measuring device, a DO density measuring device and a data processing device. Before the water-to-be-treated is irradiated with ultraviolet-ray in the TOC eliminating device (oxidation device and ion eliminating device), the deaerator controls a DO density in the water-to-be-treated according to a TOC density. Thus, an oxidizer of the TOC is maintained and impurity is decreased.

摘要翻译： 从上游侧依次设置作为具有功率可变机构的除氧装置的脱气装置，通过照射紫外线氧化TOC的氧化装置， 用于消除在氧化时产生的TOC离子的离子消除装置和颗粒消除装置。 还提供了TOC密度测量装置，DO密度测量装置和数据处理装置。 在TOC去除装置（氧化装置和离子消除装置）中用紫外线照射待处理水之前，除气器根据TOC密度控制被处理水中的DO密度。 因此，保持TOC的氧化剂并降低杂质。

公开(公告)号：US5856219A

公开(公告)日：1999-01-05

申请号：US912686

申请日：1997-08-18

申请人： Yasushi Naito ,  Yutaka Ito ,  Yuichi Hirofuji

发明人： Yasushi Naito ,  Yutaka Ito ,  Yuichi Hirofuji

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/1052 ,  H01L27/10873

摘要： The invention relates to a high-density DRAM fabrication technique for forming a source/drain contact between word lines in a self-alignment manner, with the offset length between a source region and a drain region of a peripheral transistor maintained at an adequate value. After gate electrodes (i.e. word lines) are formed, a first insulating layer, which is thin enough not to block up space defined between the word lines, is deposited. The source/drain contact is etched as deep as the first insulating layer is thick to form an extraction electrode made of polycrystalline silicon. A second insulating layer is deposited until a spacer thickness (i.e. the sum of the film thickness of the second insulating layer and the film thickness of the first insulating layer) for determining the offset length is obtained. The first and second insulating layers are etched back for a distance corresponding to the sum of the film thickness of the second insulating layer and the film thickness of the first insulating layer so that a spacer (i.e. the residue of the insulating layers) is left on the side walls of the gate electrode. An implantation of highlevel impurities is performed to form heavily doped source and drain regions of a peripheral transistor. In-cell self-align contact is made possible while maintaining the offset length of the heavily doped source and drain regions

摘要翻译： 本发明涉及用于以自对准方式在字线之间形成源极/漏极接触的高密度DRAM制造技术，其中外围晶体管的源极区域和漏极区域之间的偏移长度保持在足够的值。 在形成栅电极（即字线）之后，沉积足够薄而不能阻挡字线之间限定的空间的第一绝缘层。 源极/漏极接触被蚀刻为第一绝缘层较厚的深度，以形成由多晶硅制成的引出电极。 沉积第二绝缘层，直到获得用于确定偏移长度的间隔物厚度（即第二绝缘层的膜厚度和第一绝缘层的膜厚度之和）。 第一绝缘层和第二绝缘层被回蚀一段对应于第二绝缘层的膜厚度与第一绝缘层的膜厚之和的距离，使得间隔物（即，绝缘层的残留物）留在 栅电极的侧壁。 执行高级杂质的注入以形成外围晶体管的重掺杂源极和漏极区域。 在保持重掺杂源极和漏极区域的偏移长度的同时使单元内自对准接触成为可能

公开(公告)号：US5472906A

公开(公告)日：1995-12-05

申请号：US291914

申请日：1994-08-18

申请人： Norisato Shimizu ,  Yasushi Naito ,  Yuichi Hirofuji

发明人： Norisato Shimizu ,  Yasushi Naito ,  Yuichi Hirofuji

IPC分类号： H01L21/32 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/32 ,  H01L21/76205

摘要： A first underlaid oxide layer, a polysilicon layer, and a first silicon nitride layer are formed on a silicon substrate in this order. Using a photoresist as a mask, a portion of the first silicon nitride layer, the polysilicon layer, the first underlaid oxide layer and the silicon substrate which is to be an isolation region is etched by a depth which regulates a length of bird's beak and a threshold voltage drop of a FET adequately. After forming a second underlaid oxide layer and a second silicon nitride layer, silicon nitride side walls of more than 25 nm in thickness are formed. An isolation oxide layer is formed by selective oxidation, using the silicon nitride layer as a mask. Favorable etched depth in the step of removing the silicon substrate is one third of the thickness of the isolation oxide layer. Favorable etched depth in case of a normal FET is 20-100 nm. Thus, bird's beak length is reduced, while adequately maintaining the threshold of the transistor at formation of the isolation of transistor. In a DRAM cell pattern, isolation of not exceeding 0.2 .mu.m width can be formed.

摘要翻译： 在硅衬底上依次形成第一衬底氧化物层，多晶硅层和第一氮化硅层。 使用光致抗蚀剂作为掩模，通过调节鸟喙长度的深度蚀刻作为隔离区域的第一氮化硅层，多晶硅层，第一底层氧化物层和硅衬底的一部分， 足够的FET的阈值电压降。 在形成第二底层氧化物层和第二氮化硅层之后，形成厚度大于25nm的氮化硅侧壁。 通过使用氮化硅层作为掩模，通过选择性氧化形成隔离氧化物层。 在去除硅衬底的步骤中有利的蚀刻深度是隔离氧化物层的厚度的三分之一。 在正常FET的情况下，有利的蚀刻深度为20-100nm。 因此，在形成晶体管的隔离的同时充分保持晶体管的阈值，鸟的喙长度被减小。 在DRAM单元图案中，可以形成不超过0.2μm宽度的隔离。

公开(公告)号：US5092937A

公开(公告)日：1992-03-03

申请号：US552112

申请日：1990-07-13

申请人： Mototsugu Ogura ,  Keiichi Kagawa ,  Yuichi Hirofuji

发明人： Mototsugu Ogura ,  Keiichi Kagawa ,  Yuichi Hirofuji

IPC分类号： H01L21/304 ,  H01L21/00

CPC分类号： H01L21/67028

摘要： Semiconductors are treated with such surface-treating solutions as ultra-pure water, dilute hydrofluoric acid and an organic solvent and then subjected to removal of the surface-treating solutions remaining on the surface of the semiconductor in an inert gas atmosphere of high purity while contacting the surface of the surface-treated semiconductor only with the inert gas of high purity, whereby contamination with impurities on atom level from the atmosphere can be prevented.

摘要翻译： 半导体用诸如超纯水，稀氢氟酸和有机溶剂的表面处理溶液处理，然后在高纯度的惰性气体气氛中除去保留在半导体表面上的表面处理溶液，同时接触 表面处理的半导体的表面仅具有高纯度的惰性气体，从而可以防止来自大气的原子级杂质的污染。

公开(公告)号：US08395194B2

公开(公告)日：2013-03-12

申请号：US13238537

申请日：2011-09-21

申请人： Haruhisa Yokoyama ,  Hiroshi Sakoh ,  Kazuhiro Yamashita ,  Mitsuo Yasuhira ,  Yuichi Hirofuji

发明人： Haruhisa Yokoyama ,  Hiroshi Sakoh ,  Kazuhiro Yamashita ,  Mitsuo Yasuhira ,  Yuichi Hirofuji

IPC分类号： H01L27/148 ,  H01L27/146 ,  H01L21/00

CPC分类号： H01L27/14623 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14656

摘要： A solid-state imaging device according to the present invention is of a MOS type and includes a plurality of pixels arranged in rows and columns, and includes: a semiconductor substrate; a photodiode which is formed in the semiconductor substrate and converts, into a signal charge, light that is incident from a first main surface of the semiconductor substrate; a transfer transistor which is formed in a second main surface of the semiconductor substrate and transfers the signal charge converted by the photodiode; a light shielding film which is conductive and formed on a boundary between the pixels, above the first main surface of the semiconductor substrate; an overflow drain region electrically connected to the light shielding film and formed in the first main surface of the semiconductor substrate; and an overflow barrier region formed between the overflow drain region and the photodiode.

摘要翻译： 根据本发明的固态成像装置是MOS型的，并且包括排列成行和列的多个像素，并且包括：半导体衬底; 形成在所述半导体衬底中并将从所述半导体衬底的第一主表面入射的光转换为信号电荷的光电二极管; 传输晶体管，其形成在半导体衬底的第二主表面中并传送由光电二极管转换的信号电荷; 在半导体衬底的第一主表面之上的像素之间的边界上导电并形成的遮光膜; 与所述遮光膜电连接并形成在所述半导体衬底的所述第一主表面中的溢出漏极区域; 以及形成在溢出漏极区域和光电二极管之间的溢出阻挡区域。

公开(公告)号：US20070205488A1

公开(公告)日：2007-09-06

申请号：US11712902

申请日：2007-03-02

申请人： Jun Hirai ,  Masakatsu Suzuki ,  Ichiro Murakami ,  Yuichi Hirofuji

发明人： Jun Hirai ,  Masakatsu Suzuki ,  Ichiro Murakami ,  Yuichi Hirofuji

IPC分类号： H01L29/30

CPC分类号： H01L31/1804 ,  C30B15/04 ,  C30B29/06 ,  H01L21/3221 ,  H01L27/14687 ,  H01L27/14843 ,  H01L27/1485 ,  H01L27/14887 ,  H01L31/03921 ,  H01L31/12 ,  Y02E10/547 ,  Y02P70/521

摘要： A light-detecting device, comprising: a semiconductor substrate 101 that is composed of silicon as a base material, and contains carbon at a predetermined concentration; and an epitaxial layer 102 that is formed on the semiconductor substrate 101 and composed of silicon as a base material, the epitaxial layer 102 including a light-detecting unit (mainly 104) a predetermined distance away from the semiconductor substrate 101, wherein the semiconductor substrate 101 is formed using a crystal growth method from melt obtained by melting a material containing silicon and a material containing carbon so that carbon is contained in the semiconductor substrate 101 at the predetermined concentration.

摘要翻译： 一种光检测装置，包括：半导体衬底101，其由以硅为基底的材料构成，并含有预定浓度的碳; 以及形成在半导体衬底101上并由硅作为基底材料构成的外延层102，外延层102包括远离半导体衬底101预定距离的光检测单元（主要是104），其中半导体衬底 101是使用通过使包含硅的材料和含有碳的材料熔化而获得的熔体的晶体生长法形成的，以使得碳以预定浓度包含在半导体衬底101中。

公开(公告)号：US4459496A

公开(公告)日：1984-07-10

申请号：US251966

申请日：1981-04-03

申请人： Haruyasu Yamada ,  Toyoki Takemoto ,  Tadao Komeda ,  Tsutomu Fujita ,  Yuichi Hirofuji ,  Hiroyuki Sakai

发明人： Haruyasu Yamada ,  Toyoki Takemoto ,  Tadao Komeda ,  Tsutomu Fujita ,  Yuichi Hirofuji ,  Hiroyuki Sakai

IPC分类号： H03K19/091 ,  H03K19/092

CPC分类号： H03K19/091

摘要： In a stacked, multilayer IIL (integrated injection logic) circuit, with which power consumption can be significantly reduced, a discharging circuit constructed of an IIL constant-current circuit or of a resistor is provided for one of transistors which are used for shifting the level of a signal from an IIL circuit of a top layer to an IIL circuit of a bottom layer, so that signal transmission therebetween is prevented from deterioration. A charging circuit may be added to another transistor, while a diode may be interposed between these transistors. Additional diodes may be interposed between adjacent layers for speeding up the signal transmission from one layer to another upper layer.

摘要翻译： 在堆叠的多层IIL（集成注入逻辑）电路中，功率消耗可以显着降低，由用于移位电平的晶体管之一提供由IIL恒流电路或电阻构成的放电电路 从顶层的IIL电路到底层的IIL电路的信号，从而防止它们之间的信号传输劣化。 充电电路可以被添加到另一个晶体管，而二极管可以插在这些晶体管之间。 可以在相邻层之间插入附加的二极管，以加速从一个层到另一个上层的信号传输。