公开(公告)号：US07978043B2

公开(公告)日：2011-07-12

申请号：US12846451

申请日：2010-07-29

申请人： Yutaka Nabeshima ,  Yuichi Hirofuji

发明人： Yutaka Nabeshima ,  Yuichi Hirofuji

IPC分类号： H01F5/00

CPC分类号： H01L23/5227 ,  H01F17/0006 ,  H01F41/041 ,  H01F2017/0046 ,  H01L27/08 ,  H01L2924/0002 ,  H01Q1/2283 ,  H01Q7/00 ,  H01Q9/27 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate including at least one of a circuit and a circuit element, and an inductor element having a coil axis extending in a direction parallel to a main surface of the semiconductor substrate and disposed adjacent to the main surface. A main direction of a magnetic field induced by passing a current through the inductor element is parallel to the main surface.

摘要翻译： 半导体器件包括：半导体衬底，包括电路和电路元件中的至少一个;以及电感器元件，其具有沿与半导体衬底的主表面平行的方向延伸并且邻近主表面设置的线圈轴。 通过使电流通过电感器元件而引起的磁场的主要方向平行于主表面。

公开(公告)号：US20080278885A1

公开(公告)日：2008-11-13

申请号：US12216843

申请日：2008-07-11

申请人： Yutaka Nabeshima

发明人： Yutaka Nabeshima

IPC分类号： H01G4/00

CPC分类号： H01L27/0207 ,  H01L27/0805

摘要： A placement configuration of MIM type capacitance elements comprises a group of first capacitance elements in which the first capacitance elements as the MIM type capacitance elements are placed in tandem and a group of second capacitance elements in which the second capacitance elements as the MIM type capacitance elements are placed in tandem, wherein the group of first capacitance elements and the group of second capacitance elements are alternately placed in parallel with each other with an equal interval therebetween.

摘要翻译： MIM型电容元件的放置结构包括一组第一电容元件，其中作为MIM型电容元件的第一电容元件串联放置，以及一组第二电容元件，其中第二电容元件作为MIM型电容元件 串联放置，其中第一电容元件组和第二电容元件组交替地以彼此间隔彼此平行地放置。

公开(公告)号：US07515394B2

公开(公告)日：2009-04-07

申请号：US11349082

申请日：2006-02-08

申请人： Yutaka Nabeshima

发明人： Yutaka Nabeshima

IPC分类号： H01G4/005 ,  H01G4/228

CPC分类号： H01L27/0207 ,  H01L27/0805

摘要： A placement configuration of MIM type capacitance elements comprises a group of first capacitance elements in which the first capacitance elements as the MIM type capacitance elements are placed in tandem and a group of second capacitance elements in which the second capacitance elements as the MIM type capacitance elements are placed in tandem, wherein the group of first capacitance elements and the group of second capacitance elements are alternately placed in parallel with each other with an equal interval therebetween.

摘要翻译： MIM型电容元件的放置结构包括一组第一电容元件，其中作为MIM型电容元件的第一电容元件串联放置，以及一组第二电容元件，其中第二电容元件作为MIM型电容元件 串联放置，其中第一电容元件组和第二电容元件组交替地以彼此间隔彼此平行地放置。

公开(公告)号：US5296095A

公开(公告)日：1994-03-22

申请号：US785300

申请日：1991-10-30

申请人： Yutaka Nabeshima ,  Tokuhiko Tamaki

发明人： Yutaka Nabeshima ,  Tokuhiko Tamaki

IPC分类号： H01L21/311 ,  H01L21/00

CPC分类号： H01L21/31116

摘要： A dry etching method for dry etching a silicon oxide film or a multilayer oxide film thereof which enables formation of contact window to good dimensional precision and with stable etching configuration in the process of film etching at submicron level. A compound gas containing a C element or S element or Cl element, and F element (e.g., CF.sub.4) is used as a principal gas, and a compound gas containing a C element and two or more of H elements (e.g., CH.sub.2 F.sub.2) as an additive gas is used, in the process of dry etching silicon oxide film or a multilayer film thereof. By using principal and additive gases having good step coverage of deposit produced by plasma reaction, it is possible to eliminate any etching residue and form contact windows having stable etching configuration and good dimensional accuracy in the process of film etching at submicron level. By using a compound gas containing a greater number of H element atoms than C element atoms, the deposit on the etching side wall can be a soluble one having a low F element content, such as (C.sub.x H.sub.y)n polymer, and can be readily removed through after-etching washing.

摘要翻译： 用于干蚀刻氧化硅膜或其多层氧化物膜的干蚀刻方法，其能够在亚微米级别的膜蚀刻过程中形成接触窗以具有良好的尺寸精度和稳定的蚀刻构造。 使用含有C元素或S元素或Cl元素和F元素（例如CF 4）的复合气体作为主要气体，并且将包含C元素和两种或多种H元素（例如CH 2 F 2）的化合物气体用作 在氧化硅干法蚀刻或其多层膜的过程中，使用添加气体。 通过使用通过等离子体反应产生的沉积具有良好阶梯覆盖的主要和附加气体，可以在亚微米级的膜蚀刻过程中消除任何蚀刻残留物并形成具有稳定蚀刻构造和良好尺寸精度的接触窗口。 通过使用含有比C元素原子多的H元素原子的复合气体，蚀刻侧壁上的沉积物可以是具有低F元素含量的可溶性沉积物，例如（C x H y）n聚合物，并且可以容易地除去 通过蚀刻后的洗涤。

公开(公告)号：US07667316B2

公开(公告)日：2010-02-23

申请号：US11976963

申请日：2007-10-30

申请人： Shingo Fukamizu ,  Yutaka Nabeshima ,  Takashi Katsuyama

发明人： Shingo Fukamizu ,  Yutaka Nabeshima ,  Takashi Katsuyama

IPC分类号： H01L23/49 ,  H01L21/44

CPC分类号： H01L23/49562 ,  H01L23/4952 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05073 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05096 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/00014 ,  H01L2924/20752 ,  H01L2924/00

摘要： A semiconductor integrated circuit includes a power transistor formed on a semiconductor substrate, a plurality of first metal patterns and a plurality of second metal patterns which are formed right above the power transistor and function as a first electrode and as a second electrode of the power transistor, respectively, a plurality of first buses each electrically connected with, of a plurality of first metal patterns, a corresponding first metal pattern, a plurality of second buses each electrically connected with, of a plurality of second metal patterns, a corresponding second metal pattern, wherein one contact pad is provided to each of a plurality of first buses and a plurality of second buses.

摘要翻译： 半导体集成电路包括形成在半导体衬底上的功率晶体管，多个第一金属图案和多个第二金属图案，其形成在功率晶体管的正上方并用作第一电极和作为功率晶体管的第二电极 分别与多个第一金属图形电连接的多个第一总线，相应的第一金属图案，与多个第二金属图案电连接的多个第二总线，相应的第二金属图案 其中，一个接触垫被提供给多个第一总线和多个第二总线中的每一个。

公开(公告)号：US20090160018A1

公开(公告)日：2009-06-25

申请号：US12332720

申请日：2008-12-11

申请人： Yutaka Nabeshima ,  Masaoki Kajiyama ,  Tomohiro Matsunaga ,  Hidenori Iwadate

发明人： Yutaka Nabeshima ,  Masaoki Kajiyama ,  Tomohiro Matsunaga ,  Hidenori Iwadate

IPC分类号： H01L27/00 ,  H01L21/62 ,  H01F27/28

CPC分类号： H01L23/5227 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： An inductor includes an inductor wiring made of a metal layer and having a spiral planar shape. In a cross-sectional shape in a width direction of the inductor wiring, the inductor wiring has a larger film thickness at least in its inner side end than in its middle part.

摘要翻译： 电感器包括由金属层制成并具有螺旋形平面形状的电感器布线。 在电感器布线的宽度方向上的横截面形状中，电感器布线至少在其内侧端部比其中间部分具有更大的膜厚度。

公开(公告)号：US20080203577A1

公开(公告)日：2008-08-28

申请号：US12038060

申请日：2008-02-27

申请人： Shingo Fukamizu ,  Yutaka Nabeshima

发明人： Shingo Fukamizu ,  Yutaka Nabeshima

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L22/32 ,  G01R31/2884 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05073 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20752 ,  H01L2924/00 ,  H01L2924/20755 ,  H01L2224/45099 ,  H01L2924/00015 ,  H01L2924/2075

摘要： The semiconductor integrated circuit device includes: an active element, an interlayer insulting film, first and second metal patterns made of a first metal layer formed right above the active element, first and second buses made of a second metal layer formed right above the first metal layer, and contact pads provided on the first and second buses. The contact pad has a probe testing region and a bonding region.

摘要翻译： 半导体集成电路器件包括：有源元件，层间绝缘膜，由形成在有源元件正上方的第一金属层制成的第一和第二金属图案，由形成在第一金属正​​上方的第二金属层制成的第一和第二总线 层和在第一和第二总线上提供的接触焊盘。 接触垫具有探针测试区域和接合区域。

公开(公告)号：US20050148149A1

公开(公告)日：2005-07-07

申请号：US11011037

申请日：2004-12-15

申请人： Yutaka Nabeshima

发明人： Yutaka Nabeshima

IPC分类号： H01L21/265 ,  H01L29/93 ,  H01L29/76

CPC分类号： H01L29/93

摘要： In a method of manufacturing a variable capacitance diode according to the present invention, a mask is formed on a semiconductor substrate of a first conductive type having a low impurity concentration, a semiconductor region of the first conductive type having an intermediate impurity concentration is formed on the semiconductor substrate by means of ion implantation via an opening portion of the mask, a semiconductor region of a second conductive type having a high impurity concentration is formed in the semiconductor substrate on a surface side thereof relative to the semiconductor region of the first conductive type having the intermediate impurity concentration via the same opening portion of the mask, and the semiconductor region of the first conductive type having the intermediate impurity concentration and the semiconductor region of the second conductive type having the high impurity concentration are activated by applying a heat treatment to the semiconductor substrate. In a variable capacitance diode according to the present invention, a structure in which an annular contact layer of a first conductive type is formed in a periphery of a semiconductor region of a second conductive type having a high impurity concentration constitutes each of a plurality of units and the plurality of units is disposed in an array.

摘要翻译： 在根据本发明的可变电容二极管的制造方法中，在具有低杂质浓度的第一导电类型的半导体衬底上形成掩模，具有中间杂质浓度的第一导电类型的半导体区域形成在 通过离子注入通过掩模的开口部分的半导体衬底，在半导体衬底的相对于第一导电类型的半导体区域的表面侧上形成具有高杂质浓度的第二导电类型的半导体区域 通过掩模的相同开口部分具有中间杂质浓度，并且具有中间杂质浓度的第一导电类型的半导体区域和具有高杂质浓度的第二导电类型的半导体区域通过对 半导体衬底。 在根据本发明的可变电容二极管中，在具有高杂质浓度的第二导电类型的半导体区域的周围形成有第一导电类型的环形接触层的结构构成多个单元 并且多个单元被布置成阵列。

公开(公告)号：US5164337A

公开(公告)日：1992-11-17

申请号：US606605

申请日：1990-10-31

申请人： Hisashi Ogawa ,  Yutaka Nabeshima ,  Masanori Fukumoto

发明人： Hisashi Ogawa ,  Yutaka Nabeshima ,  Masanori Fukumoto

IPC分类号： H01L21/02 ,  H01L21/311 ,  H01L27/108

CPC分类号： H01L28/87 ,  H01L21/31111 ,  H01L27/10817 ,  H01L28/91 ,  Y10S148/014

摘要： A method of fabricating a semiconductor device is disclosed. The method comprises the steps of: forming a multi-layer film comprising two or more kinds of layers; performing first etching for patterning said multi-layer film under a first etching condition; and performing second etching for forming irregularities in the side faces of said patterned multi-layer film under a second etching condition.

摘要翻译： 公开了制造半导体器件的方法。 该方法包括以下步骤：形成包含两层或多层的多层膜; 在第一蚀刻条件下进行用于图案化所述多层膜的第一蚀刻; 并且在第二蚀刻条件下进行在所述图案化多层膜的侧面中形成凹凸的第二蚀刻。

公开(公告)号：US08179659B2

公开(公告)日：2012-05-15

申请号：US12216843

申请日：2008-07-11

申请人： Yutaka Nabeshima

发明人： Yutaka Nabeshima

IPC分类号： H01G4/005 ,  H01G4/228

CPC分类号： H01L27/0207 ,  H01L27/0805

摘要： A placement configuration of MIM type capacitance elements comprises a group of first capacitance elements in which the first capacitance elements as the MIM type capacitance elements are placed in tandem and a group of second capacitance elements in which the second capacitance elements as the MIM type capacitance elements are placed in tandem, wherein the group of first capacitance elements and the group of second capacitance elements are alternately placed in parallel with each other with an equal interval therebetween.

摘要翻译： MIM型电容元件的放置结构包括一组第一电容元件，其中作为MIM型电容元件的第一电容元件串联放置，以及一组第二电容元件，其中第二电容元件作为MIM型电容元件 串联放置，其中第一电容元件组和第二电容元件组交替地以彼此间隔彼此平行地放置。