公开(公告)号：US20110234249A1

公开(公告)日：2011-09-29

申请号：US13044717

申请日：2011-03-10

申请人： Yutaka UEMATSU ,  Hideki OSAKA ,  Satoshi NAKAMURA ,  Satoshi MURAOKA ,  Mitsuaki KATAGIRI ,  Ken IWAKURA ,  Yukitoshi HIROSE

发明人： Yutaka UEMATSU ,  Hideki OSAKA ,  Satoshi NAKAMURA ,  Satoshi MURAOKA ,  Mitsuaki KATAGIRI ,  Ken IWAKURA ,  Yukitoshi HIROSE

IPC分类号： G01R31/00

CPC分类号： G01R31/2889

摘要： An interposer to be mounted with an integrated circuit to be a test object is provided with a switch and a probe to detect an electric current corresponding to individual terminals of the integrated circuit. A test pattern signal is then inputted to the integrated circuit through a test substrate as a switch that is connected to a power supply terminal of the integrated circuit and that is turned off. If the integrated circuit normally operates and the current values of all the terminals of the integrated circuit are within a tolerance, the power supply terminal connected to the turned-off switch is identified as a terminal that may be removed.

摘要翻译： 安装有作为测试对象的集成电路的插入器设置有用于检测与集成电路的各个端子相对应的电流的开关和探头。 然后，通过作为与集成电路的电源端子连接并断开的开关的测试基板将测试图形信号输入到集成电路。 如果集成电路正常工作，并且集成电路的所有端子的电流值都在容差内，则连接到关断开关的电源端子被识别为可以被去除的端子。

公开(公告)号：US20100090325A1

公开(公告)日：2010-04-15

申请号：US12576672

申请日：2009-10-09

申请人： Yutaka UEMATSU ,  Yukitoshi HIROSE

发明人： Yutaka UEMATSU ,  Yukitoshi HIROSE

IPC分类号： H01L25/16

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In order to solve a problem of increased noise accompanying increased area of a return path in a stacked package structure, provided is a semiconductor device which is formed in a stacked package such as a PoP package, which realizes low noise without changing a package size. An additional power supply wiring that runs along a signal wiring between an upper PoP and a lower PoP is newly added in the lower PoP of a package having a PoP structure.

摘要翻译： 为了解决伴随层叠封装结构中返回路径的面积增加的噪音增加的问题，提供了形成为诸如PoP封装的堆叠封装的半导体器件，其在不改变封装尺寸的情况下实现低噪声。 在具有PoP结构的封装的下部PoP中新添加沿着上部PoP和下部PoP之间的信号布线延伸的附加电源布线。

公开(公告)号：US20090164724A1

公开(公告)日：2009-06-25

申请号：US12391783

申请日：2009-02-24

申请人： Yukitoshi HIROSE

发明人： Yukitoshi HIROSE

IPC分类号： G06F12/02

CPC分类号： G06F11/1666 ,  G06F11/141 ,  G06F11/1658 ,  G06F11/20 ,  G06F11/2094

摘要： A memory system according to the present invention copies data stored in memory modules to a hard disk device at each predetermined period, in replacing an arbitrary memory module, switches a bus from a unidirectional bus to a bi-directional bus, and at the time when an access to a memory module to be replaced is requested, accesses a storage area in the hard disk corresponding to an address space of the memory module. In addition, the memory system copies data corresponding to the address space of the memory module to be replaced from the hard disk device to a storage, and at the time when an access to the memory module is requested, accesses a storage area of the storage corresponding to the address space. Moreover, the memory system short-circuits bus connection which is disconnected by removing the memory module to be replaced.

摘要翻译： 根据本发明的存储器系统在每个预定时段将存储在存储器模块中的数据拷贝到硬盘设备，替换任意存储器模块，将总线从单向总线切换到双向总线，并且在 请求访问要更换的存储器模块，访问与存储器模块的地址空间相对应的硬盘中的存储区域。 此外，存储器系统将与要更换的存储器模块的地址空间相对应的数据从硬盘设备复制到存储器，并且在请求对存储器模块的访问时，访问存储器的存储区域 对应于地址空间。 此外，存储器系统短路总线连接，通过移除要更换的存储器模块而断开。

公开(公告)号：US20110317372A1

公开(公告)日：2011-12-29

申请号：US13164178

申请日：2011-06-20

申请人： Miho NOMOTO ,  Yukitoshi HIROSE

发明人： Miho NOMOTO ,  Yukitoshi HIROSE

IPC分类号： H05K7/00

CPC分类号： G11C5/063 ,  G11C5/04 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15192

摘要： A device includes: a wiring board having first and second surfaces opposing each other; and a plurality of memory packages on the first surface. The wiring board includes: a first set of terminals on the first surface; a plurality of second sets of terminals on the first surface; and a plurality of first signal lines. The terminals of the first set receive respective ones of a plurality of first signals supplied from a control device. Each of the second sets is provided for a corresponding one of the memory packages. The terminals of each of the second sets contact the corresponding one of the memory packages. The first signal lines extend from respective ones of the terminals of the first set while coupling respective ones of the terminals of each of the second sets. The first signal lines extend on the first surface without extending in the wiring board.

摘要翻译： 一种器件包括：具有彼此相对的第一和第二表面的布线板; 以及在所述第一表面上的多个存储器封装。 布线板包括：第一表面上的第一组端子; 在所述第一表面上的多个第二组端子; 和多条第一信号线。 第一组的端子接收从控制装置提供的多个第一信号中的相应的一个。 每个第二组被提供用于相应的一个存储器包。 每个第二组的端子与相应的一个存储器封装相接触。 第一信号线从第一组的各个端子延伸，同时连接每个第二组的各个端子。 第一信号线在第一表面上延伸而不在布线板中延伸。

公开(公告)号：US20090065774A1

公开(公告)日：2009-03-12

申请号：US12264301

申请日：2008-11-04

申请人： Yukitoshi HIROSE

发明人： Yukitoshi HIROSE

IPC分类号： H01L23/48

CPC分类号： H01L22/32 ,  H01L23/50 ,  H01L23/5382 ,  H01L24/17 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention is applied to a multilayer semiconductor device including a plurality of layered semiconductor chips. At least one of the plurality of layered semiconductor chips comprises a pad that is not connected to any external circuit terminal of the multilayer semiconductor device. The multilayer semiconductor device further comprises a separating element that connects the pad to a test stub line when each semiconductor chip is tested and separates the pad from the test stub line during the normal operation.

摘要翻译： 本发明应用于包括多层分层半导体芯片的多层半导体器件。 所述多个分层半导体芯片中的至少一个包括不连接到所述多层半导体器件的任何外部电路端子的焊盘。 所述多层半导体器件还包括分离元件，其在测试每个半导体芯片时将所述焊盘连接到测试短截线，并且在正常操作期间将焊盘与测试短截线分离。

公开(公告)号：US20070290317A1

公开(公告)日：2007-12-20

申请号：US11837820

申请日：2007-08-13

申请人： Yukitoshi HIROSE

发明人： Yukitoshi HIROSE

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device includes an interface chip and a plurality of DRAM chips consecutively layered on the interface chip. A plurality of source electrodes, a plurality of ground electrodes, and a plurality of signal electrodes penetrate DRAM chips and interconnect the DRAM chips to the interface chip, which is connected to an external circuit. Each source electrode, a corresponding signal electrode and a corresponding ground electrode are arranged adjacent to one another in this order to reduce electromagnetic noise during operation of the DRAM chip.

摘要翻译： 半导体器件包括在接口芯片上连续分层的接口芯片和多个DRAM芯片。 多个源电极，多个接地电极和多个信号电极穿过DRAM芯片并将DRAM芯片互连到与外部电路连接的接口芯片。 每个源电极，相应的信号电极和对应的接地电极按照这个顺序相互排列，以减少DRAM芯片工作期间的电磁噪声。