公开(公告)号：US08487433B2

公开(公告)日：2013-07-16

申请号：US13192065

申请日：2011-07-27

申请人： Yu Hasegawa ,  Mitsuaki Katagiri

发明人： Yu Hasegawa ,  Mitsuaki Katagiri

IPC分类号： H01L23/498 ,  H01L23/522

CPC分类号： H01L23/49811 ,  H01L23/13 ,  H01L23/538 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/4911 ,  H01L2224/49175 ,  H01L2224/49426 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83192 ,  H01L2224/85051 ,  H01L2224/85186 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/92147 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/4554

摘要： A device includes a substrate, a semiconductor chip, first and second pads, and a first wiring layer. The substrate includes first and second surfaces. The semiconductor chip includes third and fourth surfaces. The third surface faces toward the first surface. The first and second pads are provided on the third surface. The first and second pads are connected to each other. The first wiring layer is provided on the second surface of the substrate. The first wiring layer is connected to the first pad.

公开(公告)号：US08372693B2

公开(公告)日：2013-02-12

申请号：US13538654

申请日：2012-06-29

申请人： Mitsuaki Katagiri ,  Hisashi Tanie ,  Jun Kayamori ,  Dai Sasaki ,  Hiroshi Moriya

发明人： Mitsuaki Katagiri ,  Hisashi Tanie ,  Jun Kayamori ,  Dai Sasaki ,  Hiroshi Moriya

IPC分类号： H01L23/02 ,  H01L23/485 ,  H01L25/10

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/32 ,  H01L24/50 ,  H01L24/86 ,  H01L25/0657 ,  H01L2224/29101 ,  H01L2224/29191 ,  H01L2225/0652 ,  H01L2225/06555 ,  H01L2225/06579 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/30105 ,  H01L2924/3511 ,  H01L2924/00

摘要： In a stacked-type semiconductor device, a first semiconductor device and at least one second semiconductor device are stacked. The first semiconductor device includes a wiring board and a first semiconductor chip mounted on the wiring board. The second semiconductor device includes a wiring board and a second semiconductor chip mounted on the wiring board. The thickness of the second semiconductor chip of each second semiconductor device is thicker than the thickness of the first semiconductor chip.

摘要翻译： 在层叠型半导体器件中，堆叠第一半导体器件和至少一个第二半导体器件。 第一半导体器件包括布线板和安装在布线板上的第一半导体芯片。 第二半导体器件包括布线板和安装在布线板上的第二半导体芯片。 每个第二半导体器件的第二半导体芯片的厚度比第一半导体芯片的厚度厚。

公开(公告)号：US08362614B2

公开(公告)日：2013-01-29

申请号：US11247215

申请日：2005-10-12

申请人： Mitsuaki Katagiri ,  Hiroya Shimizu ,  Fumiyuki Osanai ,  Yasushi Takahashi ,  Seiji Narui

发明人： Mitsuaki Katagiri ,  Hiroya Shimizu ,  Fumiyuki Osanai ,  Yasushi Takahashi ,  Seiji Narui

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/50 ,  H01L23/49838 ,  H01L2224/4824 ,  H01L2924/13091 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device has a semiconductor chip in which a plurality of semiconductor components and a plurality of pads are arranged, a plurality of external connection contacts arranged in grids, and a plurality of wires for electrically connecting the pads and the external connection contacts. The pads include a plurality of pad groups including a pair of electrode pads connected to the plurality of semiconductor components in common and a plurality of signal pads respectively connected to the semiconductor components connected to the electrode pads. In each pad group, each signal pad is arranged adjacently to one of the electrode pads; and each wire extending from each signal pad is extended along a wire extended from the electrode pad adjacent to each signal pad.

摘要翻译： 半导体器件具有其中布置有多个半导体部件和多个焊盘的半导体芯片，布置在栅格中的多个外部连接触点，以及用于电连接焊盘和外部连接触点的多条引线。 焊盘包括多个焊盘组，其包括连接到共同的多个半导体部件的一对电极焊盘和分别连接到连接到电极焊盘的半导体部件的多个信号焊盘。 在每个焊盘组中，每个信号焊盘被布置成与电极焊盘之一相邻; 并且从每个信号焊盘延伸的每条焊丝沿着与每个信号焊盘相邻的电极焊盘延伸的焊丝延伸。

公开(公告)号：US20120146242A1

公开(公告)日：2012-06-14

申请号：US13323246

申请日：2011-12-12

申请人： Hiroyuki Fujishima ,  Dai Sasaki ,  Satoshi Isa ,  Mitsuaki Katagiri

发明人： Hiroyuki Fujishima ,  Dai Sasaki ,  Satoshi Isa ,  Mitsuaki Katagiri

IPC分类号： H01L23/498

CPC分类号： H01L21/563 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83192 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012

摘要： A semiconductor device includes a wiring board, a stack of semiconductor chips, and a first sealing member. The wiring board has a first surface. The wiring board includes a first insulating layer formed over the first surface. The first insulating layer has a first opening. The stack of semiconductor chips is mounted over the first surface of the wiring board. The stack of semiconductor chips includes a first semiconductor chip. The first semiconductor chip is closer to the wiring board than the other semiconductor chips. The first sealing member seals at least the first semiconductor chip. The first sealing member includes a protruding portion. The first opening of the insulating layer faces toward the protruding portion of the first sealing member.

摘要翻译： 半导体器件包括布线板，半导体芯片堆叠和第一密封构件。 布线板具有第一表面。 布线板包括形成在第一表面上的第一绝缘层。 第一绝缘层具有第一开口。 半导体芯片的堆叠被安装在布线板的第一表面上。 半导体芯片堆叠包括第一半导体芯片。 第一半导体芯片比其他半导体芯片更接近布线板。 第一密封构件至少密封第一半导体芯片。 第一密封构件包括突出部。 绝缘层的第一开口朝向第一密封构件的突出部分。

公开(公告)号：US20110084395A1

公开(公告)日：2011-04-14

申请号：US12923712

申请日：2010-10-05

申请人： Hiromasa Takeda ,  Satoshi Isa ,  Mitsuaki Katagiri ,  Ken Iwakura ,  Yu Hasegawa

发明人： Hiromasa Takeda ,  Satoshi Isa ,  Mitsuaki Katagiri ,  Ken Iwakura ,  Yu Hasegawa

IPC分类号： H01L23/48

CPC分类号： H01L24/50 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor chip and a package substrate on which the semiconductor chip is mounted. The package substrate has internal terminals connected to the semiconductor chip, front surface wirings connected to the internal terminals, rear surface wirings connected to external electrodes, and contacts connecting the front surface wiring and rear surface wiring. Out of the plurality of contact, some contacts included in the wirings for signal transmission are disposed near the internal terminals. Thus, a signal led out from the semiconductor chip is immediately taken away from the chip mounting surface of the package substrate. This reduces the floating capacitance between the wirings on the package substrate and chip, thereby improving the signal quality.

摘要翻译： 半导体器件包括其上安装半导体芯片的半导体芯片和封装衬底。 封装衬底具有连接到半导体芯片的内部端子，连接到内部端子的前表面布线，连接到外部电极的后表面布线以及连接前表面布线和背面布线的触点。 在多个接触中，用于信号传输的布线中包括的一些触点设置在内部端子附近。 因此，从半导体芯片引出的信号立即从封装基板的芯片安装表面取走。 这降低了封装衬底和芯片之间的布线之间的浮动电容，从而提高了信号质量。

公开(公告)号：US07777350B2

公开(公告)日：2010-08-17

申请号：US12219839

申请日：2008-07-29

申请人： Dai Sasaki ,  Mitsuaki Katagiri ,  Satoshi Isa

发明人： Dai Sasaki ,  Mitsuaki Katagiri ,  Satoshi Isa

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L23/02 ,  H01L27/146 ,  H01L27/148

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L24/06 ,  H01L24/45 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/4911 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor stack package includes a first printed wiring board; a plurality of semiconductor chips stacked on the first printed wiring board, wherein among the semiconductor chips, the uppermost semiconductor chip has an electrode pad for providing power supply, a ground pad for providing grounding, and a signal pad for signal transmission in a center area on the upper surface of the chip; connection lands formed on the first printed wiring board on the outside of the stacked semiconductor chips; a wiring extension part which is formed on the uppermost semiconductor chip, and has wiring circuits extending from the center to the periphery thereof, wherein at least one of the electrode pad and the ground pad is electrically connected to one end of one of the wiring circuits; and a wire for connecting the other end of the relevant wiring circuit of the wiring extension part and one of the connection lands on the first printed wiring board.

摘要翻译： 半导体堆叠封装包括第一印刷线路板; 堆叠在第一印刷线路板上的多个半导体芯片，其中在半导体芯片中，最上半导体芯片具有用于提供电源的电极焊盘，用于提供接地的接地焊盘和用于在中心区域中进行信号传输的信号焊盘 在芯片的上表面; 在叠层半导体芯片的外侧的第一印刷布线板上形成的连接焊盘; 布线延伸部，形成在最上半导体芯片上，并且具有从中心延伸到其周边的布线电路，其中电极焊盘和接地焊盘中的至少一个电连接到一个布线电路的一端 ; 以及用于连接布线延伸部分的相关布线电路的另一端和第一印刷布线板上的一个连接焊盘的导线。

公开(公告)号：US20100193929A1

公开(公告)日：2010-08-05

申请号：US12686567

申请日：2010-01-13

申请人： Ken IWAKURA ,  Mitsuaki Katagiri ,  Satoshi Isa ,  Dai Sasaki

发明人： Ken IWAKURA ,  Mitsuaki Katagiri ,  Satoshi Isa ,  Dai Sasaki

IPC分类号： H01L23/522

CPC分类号： H01L23/49833 ,  H01L23/3128 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/32145 ,  H01L2924/00012

摘要： A semiconductor device includes a package board, first connectors, and a first multi-layered structure. The package board has first and second regions. The first connectors are in the first region. The first multi-layered structure includes a first semiconductor chip, a wiring board, and second to fifth connectors. The first semiconductor chip has first and second surfaces. The first surface covers the second region. The wiring board has third and fourth surfaces. The third surface is fixed to the second surface. The second to fourth connectors are in the center regions of the second to fourth surfaces, respectively. The fifth connectors are aligned along opposing two sides of the fourth surface. The second connectors electrically connect to the third connectors. The third connectors electrically connect to the fourth and fifth connectors. The first connectors electrically connect to the fourth and fifth connectors.

摘要翻译： 半导体器件包括封装板，第一连接器和第一多层结构。 封装板具有第一和第二区域。 第一个连接器位于第一个区域。 第一多层结构包括第一半导体芯片，布线板和第二至第五连接器。 第一半导体芯片具有第一和第二表面。 第一个表面覆盖第二个区域。 布线板具有第三和第四表面。 第三表面固定到第二表面。 第二至第四连接器分别位于第二至第四表面的中心区域。 第五连接器沿着第四表面的相对的两侧排列。 第二连接器电连接到第三连接器。 第三连接器电连接到第四和第五连接器。 第一连接器电连接到第四和第五连接器。

公开(公告)号：US07694245B2

公开(公告)日：2010-04-06

申请号：US11710965

申请日：2007-02-27

申请人： Mitsuaki Katagiri ,  Satoshi Nakamura ,  Takashi Suga ,  Yoji Nishio ,  Satoshi Isa ,  Satoshi Itaya

发明人： Mitsuaki Katagiri ,  Satoshi Nakamura ,  Takashi Suga ,  Yoji Nishio ,  Satoshi Isa ,  Satoshi Itaya

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  H01L23/50 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method for designing a semiconductor package is disclosed, wherein the semiconductor package comprises a semiconductor chip and an adjustment target. A first target variable is calculated in consideration of a first transition state where an output level of the semiconductor chip changes from a low level to a high level. A second target variable is calculated in consideration of a second transition state where an output level of the semiconductor chip changes from the high level to the low level. Inferior one of the first and the second target variables is selected as a main target variable. The main target variable and a predetermined constraint represented in frequency domain are compared to decide design guidelines for the adjustment target.

摘要翻译： 公开了一种用于设计半导体封装的方法，其中半导体封装包括半导体芯片和调整对象。 考虑到半导体芯片的输出电平从低电平变为高电平的第一转变状态来计算第一目标变量。 考虑到半导体芯片的输出电平从高电平变为低电平的第二过渡状态来计算第二目标变量。 选择第一和第二目标变量之一作为主要目标变量。 比较主要目标变量和在频域中表示的预定约束，以决定调整目标的设计指南。

公开(公告)号：US20090327981A1

公开(公告)日：2009-12-31

申请号：US12457930

申请日：2009-06-25

申请人： Satoshi Nakamura ,  Tsutomu Hara ,  Mitsuaki Katagiri ,  Yukitoshi Hirose ,  Satoshi Itaya ,  Ken Iwakura

发明人： Satoshi Nakamura ,  Tsutomu Hara ,  Mitsuaki Katagiri ,  Yukitoshi Hirose ,  Satoshi Itaya ,  Ken Iwakura

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F2217/78 ,  H05K1/181 ,  H05K3/0005

摘要： Correction circuit models are acquired for correcting electrical characteristic parameters that change upon mounting on a board. The correction circuit models are added to a separate model that represents a separate semiconductor device in isolation to create a semiconductor device model that represents the semiconductor device in a board-mounted state. An equivalent circuit model that represents an adjustment-object system is connected to the semiconductor device model that was created, and based on the semiconductor device model to which the equivalent circuit model is connected, adjustment-object values relating to the adjustment-object system are calculated. These adjustment-object values are compared with limit values that were determined in advance, and based on the results of comparison, a design guide is determined for adjusting the adjustment-object system.

摘要翻译： 获取校正电路模型，用于校正在电路板上安装时变化的电特性参数。 校正电路模型被添加到单独的模型中，该模型表示隔离的单独的半导体器件以产生表示板安装状态的半导体器件的半导体器件模型。 表示调整对象系统的等效电路模型连接到所创建的半导体器件模型，并且基于与等效电路模型相连接的半导体器件模型，与调整对象系统相关的调整对象值为 计算。 将这些调整对象值与预先确定的限制值进行比较，并且基于比较结果，确定调整对象系统的设计指南。

公开(公告)号：US20090140412A1

公开(公告)日：2009-06-04

申请号：US12363166

申请日：2009-01-30

申请人： Mitsuaki Katagiri ,  Hisashi Tanie

发明人： Mitsuaki Katagiri ,  Hisashi Tanie

IPC分类号： H01L23/49

CPC分类号： H01L24/50 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L2224/50 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/3011

摘要： A semiconductor chip is mounted on a flexible wiring board through the interposition of an elastmer. The flexible wiring board is made up of a tape on which wiring is fixed. A part of the wiring is projected beyond the edge of the tape, extended in the direction of the thickness of the elastmer and connected to an electrode of the semiconductor chip. The edge of the tape beyond which the wiring is projected protrudes beyond the edge of the elastmer by a length no smaller than the thickness of the elastmer.

摘要翻译： 通过插入弹性体将半导体芯片安装在柔性布线板上。 柔性布线板由布线固定的胶带组成。 布线的一部分突出超过带的边缘，沿着弹性体的厚度方向延伸并连接到半导体芯片的电极。 布线超过其的投影边缘突出超过弹性体边缘的长度不小于弹性体的厚度。