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公开(公告)号:US20100191920A1
公开(公告)日:2010-07-29
申请号:US12360533
申请日:2009-01-27
申请人: Zhen Fang , David J. Harriman , Michael W. Leddige
发明人: Zhen Fang , David J. Harriman , Michael W. Leddige
CPC分类号: G06F12/0835 , G06F12/0888 , G06F12/1027
摘要: In one embodiment, the present invention includes a method for receiving a memory request from a device coupled to an input/output (IO) interconnect, accessing a mapping table associated with the IO interconnect to determine if an address range including an address of the memory request is coherent, and if so, sending the memory request and a coherency indicator to indicate the coherent state of data at the address, otherwise sending the memory request and the coherency indicator to indicate a non-coherent state. Other embodiments are described and claimed.
摘要翻译: 在一个实施例中,本发明包括一种用于从耦合到输入/输出(IO)互连的设备接收存储器请求的方法,访问与IO互连关联的映射表,以确定包括存储器的地址的地址范围 请求是一致的,如果是,则发送存储器请求和一致性指示符以指示地址处的数据的相干状态,否则发送存储器请求和一致性指示符以指示非相干状态。 描述和要求保护其他实施例。
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公开(公告)号:US08631208B2
公开(公告)日:2014-01-14
申请号:US12360533
申请日:2009-01-27
申请人: Zhen Fang , David J. Harriman , Michael W. Leddige
发明人: Zhen Fang , David J. Harriman , Michael W. Leddige
IPC分类号: G06F13/00
CPC分类号: G06F12/0835 , G06F12/0888 , G06F12/1027
摘要: In one embodiment, the present invention includes a method for receiving a memory request from a device coupled to an input/output (IO) interconnect, accessing a mapping table associated with the IO interconnect to determine if an address range including an address of the memory request is coherent, and if so, sending the memory request and a coherency indicator to indicate the coherent state of data at the address, otherwise sending the memory request and the coherency indicator to indicate a non-coherent state. Other embodiments are described and claimed.
摘要翻译: 在一个实施例中,本发明包括一种用于从耦合到输入/输出(IO)互连的设备接收存储器请求的方法,访问与IO互连关联的映射表,以确定包括存储器的地址的地址范围 请求是一致的,如果是,则发送存储器请求和一致性指示符以指示地址处的数据的相干状态,否则发送存储器请求和一致性指示符以指示非相干状态。 描述和要求保护其他实施例。
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3.
公开(公告)号:US08649262B2
公开(公告)日:2014-02-11
申请号:US12241619
申请日:2008-09-30
IPC分类号: H04L12/26
CPC分类号: H04L12/10 , H04L41/0896
摘要: According to some embodiments, first and second processing elements may be provided on a die, and there may be a plurality of potential communication links between the first and second processing elements. Moreover, control logic may be provided on the die to dynamically activate at least some of the potential communication links (e.g., based on a current bandwidth appropriate between the first and second processing elements).
摘要翻译: 根据一些实施例,第一和第二处理元件可以设置在管芯上,并且在第一和第二处理元件之间可以存在多个潜在的通信链路。 此外,可以在管芯上提供控制逻辑以动态激活潜在的通信链路中的至少一些(例如,基于在第一和第二处理元件之间适当的当前带宽)。
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4.
公开(公告)号:US08099687B2
公开(公告)日:2012-01-17
申请号:US11899497
申请日:2007-09-05
IPC分类号: G06F17/50
CPC分类号: H01L23/49816 , G11C5/02 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H05K1/181 , H05K2201/10159 , H05K2201/10734 , H05K2203/1572 , Y02P70/611
摘要: A memory module has an array of connections. The array of connections is arranged in rows and columns such that there are first and second outer columns. Connections in the first and second outer columns can be interchanged to optimize double-side module placement on a substrate.
摘要翻译: 存储器模块具有连接阵列。 连接阵列以行和列排列,使得存在第一和第二外部列。 可以互换第一和第二外柱中的连接,以优化在基板上的双面模块放置。
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公开(公告)号:US07402048B2
公开(公告)日:2008-07-22
申请号:US11393540
申请日:2006-03-30
申请人: Pascal C. Meier , Michael W. Leddige , Mohiuddin Mazumder , Mark Trobough , Alok Tripathi , Ven R. Holalkere
发明人: Pascal C. Meier , Michael W. Leddige , Mohiuddin Mazumder , Mark Trobough , Alok Tripathi , Ven R. Holalkere
IPC分类号: H01R12/00
CPC分类号: H01R12/52 , H05K1/147 , H05K3/222 , H05K2201/044 , H05K2201/10189 , H05K2201/10325 , H05K2201/10719
摘要: An apparatus includes a printed circuit board (PCB) and a first flexible conductive cable (“flex cable”) secured to the PCB. The apparatus also includes a daughter card having an end adjacent to the PCB and a second flex cable secured to the daughter card. The apparatus further includes a connector which provides an electrically conductive connection between the first flex cable and the second flex cable. The connector is positioned to sandwich a portion of the first flex cable between the connector and the PCB.
摘要翻译: 一种装置包括固定到PCB的印刷电路板(PCB)和第一柔性导电电缆(“柔性电缆”)。 该装置还包括具有邻近PCB的端部的子卡和固定到子卡的第二柔性电缆。 该装置还包括连接器,其在第一柔性电缆和第二柔性电缆之间提供导电连接。 连接器被定位成将第一柔性电缆的一部分夹在连接器和PCB之间。
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6.
公开(公告)号:US07194572B2
公开(公告)日:2007-03-20
申请号:US10638069
申请日:2003-08-08
IPC分类号: G06F12/00
CPC分类号: G06F13/4239 , G11C5/04
摘要: Embodiments of the invention provide a memory command and address (CA) bus architecture that can accommodate higher CA data output frequencies with reduced signal degradation. For one embodiment of the invention the CA is divided on the motherboard and a CA signal component routed to each of two dual in-line memory modules (DIMMs) of a two-DIMM/channel memory bus design. The CA signal component on each DIMM is then routed sequentially through each dynamic random access memory (DRAM) chip on the respective DIMM. In one embodiment, after routing through each DRAM, the CA signal is terminated on the DIMM. In an alternative embodiment, the CA signal is terminated on the die at the last DRAM of each respective DIMM.
摘要翻译: 本发明的实施例提供了一种存储器命令和地址(CA)总线架构,其可以适应具有降低的信号劣化的较高CA数据输出频率。 对于本发明的一个实施例,CA在主板上被划分,并且CA信号分量被路由到两个DIMM /通道存储器总线设计的两个双列直插式存储器模块(DIMM)中的每一个。 然后,每个DIMM上的CA信号分量依次通过相应DIMM上的每个动态随机存取存储器(DRAM)芯片。 在一个实施例中,在路由每个DRAM之后,CA信号在DIMM上终止。 在替代实施例中,CA信号在每个相应的DIMM的最后一个DRAM处终止在管芯上。
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公开(公告)号:US6144576A
公开(公告)日:2000-11-07
申请号:US136797
申请日:1998-08-19
摘要: A serial memory architecture. A memory subsystem includes a bus and a first memory module coupled to the bus. The first memory module has a first connector to receive bus signals from the bus and a second connector to output the bus signals. A second memory module has a first connector to receive the bus signals from the second connector of the first memory module. The bus signals are thereby routed through the memory modules in a serial manner. In one embodiment the memory modules include one or more 90.degree. routing paths between connectors and the devices of the memory modules. In one embodiment, trace lengths are matched.
摘要翻译: 串行存储器架构。 存储器子系统包括总线和耦合到总线的第一存储器模块。 第一存储器模块具有用于从总线接收总线信号的第一连接器和用于输出总线信号的第二连接器。 第二存储器模块具有用于从第一存储器模块的第二连接器接收总线信号的第一连接器。 因此,总线信号以串行方式路由存储器模块。 在一个实施例中,存储器模块包括连接器和存储器模块的装置之间的一个或多个90°路由路径。 在一个实施例中,迹线长度匹配。
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8.
公开(公告)号:US08438515B2
公开(公告)日:2013-05-07
申请号:US13339525
申请日:2011-12-29
IPC分类号: G06F17/50
CPC分类号: H01L23/49816 , G11C5/02 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H05K1/181 , H05K2201/10159 , H05K2201/10734 , H05K2203/1572 , Y02P70/611
摘要: A memory module has an array of connections. The array of connections is arranged in rows and columns such that there are first and second outer columns. Connections in the first and second outer columns can be interchanged to optimize double-side module placement on a substrate. Other embodiments are also disclosed and claimed.
摘要翻译: 存储器模块具有连接阵列。 连接阵列以行和列排列,使得存在第一和第二外部列。 可以互换第一和第二外柱中的连接,以优化在基板上的双面模块放置。 还公开并要求保护其他实施例。
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公开(公告)号:US20120199973A1
公开(公告)日:2012-08-09
申请号:US13339525
申请日:2011-12-29
IPC分类号: H01L23/498
CPC分类号: H01L23/49816 , G11C5/02 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H05K1/181 , H05K2201/10159 , H05K2201/10734 , H05K2203/1572 , Y02P70/611
摘要: A memory module has an array of connections. The array of connections is arranged in rows and columns such that there are first and second outer columns. Connections in the first and second outer columns can be interchanged to optimize double-side module placement on a substrate. Other embodiments are also disclosed and claimed.
摘要翻译: 存储器模块具有连接阵列。 连接阵列以行和列排列,使得存在第一和第二外部列。 可以互换第一和第二外柱中的连接,以优化在基板上的双面模块放置。 还公开并要求保护其他实施例。
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公开(公告)号:US20080266778A1
公开(公告)日:2008-10-30
申请号:US12052804
申请日:2008-03-21
CPC分类号: G11C5/025 , G11C5/04 , H05K1/0298 , H05K1/181 , H05K2201/09227 , H05K2201/10159 , Y02P70/611
摘要: In some embodiments a memory module circuit board includes a first surface adapted to couple a first plurality of memory devices, a plurality of signal lines, and a command and address bus coupled to the signal lines. The command and address bus is routed from the signal lines and adapted to couple to at least one of the first plurality of memory devices in a manner that does not require the command and address bus lines to turn more than approximately ninety degrees before coupling to the at least one of the first plurality of memory devices. Other embodiments are described and claimed.
摘要翻译: 在一些实施例中,存储器模块电路板包括适于耦合第一多个存储器件,多条信号线以及耦合到信号线的命令和地址总线的第一表面。 命令和地址总线从信号线路由并且适于以不要求命令和地址总线转过多于九十度的方式耦合到第一多个存储器件中的至少一个,在耦合到 所述第一多个存储器件中的至少一个。 描述和要求保护其他实施例。
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