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公开(公告)号：US06902258B2
公开(公告)日：2005-06-07
申请号：US10954065
申请日：2004-09-28
IPC分类号： H01L21/8238 , B41J2/05 , H01L21/00 , H01L23/48
CPC分类号： H01L21/823892 , H01L21/823807 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) is formed on a substrate. The IC has a first well having a first dopant concentration that includes a second conductivity low-voltage transistor. The IC also has a second well having a dopant concentration equal to the first dopant concentration that includes a first conductivity high-voltage transistor. In addition, the IC has a third well having a second dopant concentration of an opposite type than the first well that includes a first conductivity low-voltage transistor. The first conductivity low-voltage transistor and the second conductivity low-voltage transistor are created without a threshold voltage (Vt) implant.
摘要翻译： 在基板上形成集成电路（IC）。 IC具有第一阱，其具有包括第二导电低压晶体管的第一掺杂剂浓度。 IC还具有掺杂浓度等于包括第一导电高压晶体管的第一掺杂剂浓度的第二阱。 此外，IC具有第三阱，其具有与包括第一导电低压晶体管的第一阱相反类型的第二掺杂剂浓度。 产生第一导电低压晶体管和第二导电低电压晶体管，而没有阈值电压（V OUT）。
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公开(公告)号：US06818494B1
公开(公告)日：2004-11-16
申请号：US09817703
申请日：2001-03-26
IPC分类号： H01L218238
CPC分类号： H01L21/823892 , H01L21/823807 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) is formed on a substrate. The IC has a first well having a first dopant concentration that includes a second conductivity low-voltage transistor. The IC also has a second well having a dopant concentration equal to the first dopant concentration that includes a first conductivity high-voltage transistor. In addition, the IC has a third well having a second dopant concentration of an opposite type than the first well that includes a first conductivity low-voltage transistor. The first conductivity low-voltage transistor and the second conductivity low-voltage transistor are created without a threshold voltage (Vt) implant.
摘要翻译： 在基板上形成集成电路（IC）。 IC具有第一阱，其具有包括第二导电低压晶体管的第一掺杂剂浓度。 IC还具有掺杂浓度等于包括第一导电高压晶体管的第一掺杂剂浓度的第二阱。 此外，IC具有第三阱，其具有与包括第一导电低压晶体管的第一阱相反类型的第二掺杂剂浓度。 产生第一导电低压晶体管和第二导电低压晶体管，而没有阈值电压（Vt）植入。
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公开(公告)号：US20050041070A1
公开(公告)日：2005-02-24
申请号：US10954065
申请日：2004-09-28
IPC分类号： H01L21/8238 , B41J2/05
CPC分类号： H01L21/823892 , H01L21/823807 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) is formed on a substrate. The IC has a first well having a first dopant concentration that includes a second conductivity low-voltage transistor. The IC also has a second well having a dopant concentration equal to the first dopant concentration that includes a first conductivity high-voltage transistor. In addition, the IC has a third well having a second dopant concentration of an opposite type than the first well that includes a first conductivity low-voltage transistor. The first conductivity low-voltage transistor and the second conductivity low-voltage transistor are created without a threshold voltage (Vt) implant.
摘要翻译： 在基板上形成集成电路（IC）。 IC具有第一阱，其具有包括第二导电低压晶体管的第一掺杂剂浓度。 IC还具有掺杂浓度等于包括第一导电高压晶体管的第一掺杂剂浓度的第二阱。 此外，IC具有第三阱，其具有与包括第一导电低压晶体管的第一阱相反类型的第二掺杂剂浓度。 产生第一导电低压晶体管和第二导电低压晶体管，而没有阈值电压（Vt）植入。
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公开(公告)号：US07150516B2
公开(公告)日：2006-12-19
申请号：US10977091
申请日：2004-10-29
申请人： Simon Dodd , S. Jonathan Wang , Dennis W. Tom , Frank R. Bryant , Terry E. McMahon , Richard Todd Miller , Gregory T. Hindman
发明人： Simon Dodd , S. Jonathan Wang , Dennis W. Tom , Frank R. Bryant , Terry E. McMahon , Richard Todd Miller , Gregory T. Hindman
IPC分类号： B41J2/05
CPC分类号： B41J2/1628 , B41J2/14129 , B41J2/1603 , B41J2202/13 , H01L2924/0002 , H01L2924/00
摘要： A fluid ejection device including: a substrate having a first surface having an non-doped region; a first insulative material disposed on a portion of the first surface, the first insulative material having a plurality of openings forming a path to the first surface; a first conductive material disposed on the first insulative material, the first conductive material being disposed so that the plurality of openings are substantially free of the first conductive material; a second insulative material disposed on the first conductive material and portions of the first insulative material, the second insulative material being disposed so that the plurality of openings are substantial free of the second insulative material and a second conductive material being disposed on second insulative material and within plurality of openings so that some of the second conductive material disposed upon the second insulative material is in electrical contact with the non-doped region on the substrate.
摘要翻译： 一种流体喷射装置，包括：具有第一表面和非掺杂区域的基板; 第一绝缘材料，设置在所述第一表面的一部分上，所述第一绝缘材料具有形成到所述第一表面的路径的多个开口; 设置在所述第一绝缘材料上的第一导电材料，所述第一导电材料设置成使得所述多个开口基本上不含所述第一导电材料; 设置在第一导电材料上的第二绝缘材料和第一绝缘材料的部分，第二绝缘材料设置成使得多个开口基本上不含第二绝缘材料，第二导电材料设置在第二绝缘材料上 并且在多个开口内，使得设置在第二绝缘材料上的一些第二导电材料与衬底上的非掺杂区域电接触。
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公开(公告)号：US07781843B1
公开(公告)日：2010-08-24
申请号：US11652182
申请日：2007-01-11
申请人： James Weaver , S. Jonathan Wang , John Chen , Sadiq Bengali , Edward Enciso , Tom Cooney
发明人： James Weaver , S. Jonathan Wang , John Chen , Sadiq Bengali , Edward Enciso , Tom Cooney
IPC分类号： H01L21/335
CPC分类号： H01L21/823418 , H01L21/823462 , H01L21/823814 , H01L21/823857 , H01L27/0922 , H01L29/7833
摘要： High-voltage CMOS devices and low-voltage CMOS devices are integrated on a common substrate by forming a sacrificial film over at least active device areas, lithographically defining device active regions of the high-voltage CMOS devices, implanting dopants selectively through the sacrificial film into the lithographically defined device active regions of the high-voltage CMOS devices, diffusing the implanted dopants, removing the sacrificial film, and subsequently forming low-voltage CMOS devices.
摘要翻译： 高压CMOS器件和低电压CMOS器件集成在公共衬底上，通过在至少有源器件区域上形成牺牲膜，光刻地限定高电压CMOS器件的器件有源区，通过牺牲膜选择性地注入掺杂物到 光刻定义的高压CMOS器件的器件有源区，扩散注入的掺杂剂，去除牺牲膜，随后形成低电压CMOS器件。
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公开(公告)号：US06879525B2
公开(公告)日：2005-04-12
申请号：US10001680
申请日：2001-10-31
CPC分类号： G11C13/0004 , G11C11/56 , G11C11/5678 , G11C13/0064 , G11C13/0069 , G11C2013/0066 , G11C2013/009 , G11C2213/72
摘要： An integrated circuit includes an array of state-change devices, first and second decoder circuits for selecting a particular state-change device. A voltage source is coupled to the first decoder circuit and sense circuitry is coupled to the second decoder to receive an electrical parameter from the selected state-change device and to detect a particular value of the electrical parameter. A control circuit is coupled to the voltage source, the first and second decoders, and the sense circuitry to select a first voltage from the voltage source to alter the selected state-change device and to select a second voltage from the voltage source when the sense circuitry detects the particular value of the electrical parameter.
摘要翻译： 集成电路包括状态变换器件阵列，用于选择特定状态改变器件的第一和第二解码器电路。 电压源耦合到第一解码器电路，并且感测电路耦合到第二解码器以从所选择的状态改变装置接收电参数并且检测电参数的特定值。 控制电路耦合到电压源，第一和第二解码器以及感测电路，以从电压源选择第一电压以改变所选择的状态改变装置，并且当感测时选择来自电压源的第二电压 电路检测电参数的特定值。
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公开(公告)号：US07543917B2
公开(公告)日：2009-06-09
申请号：US11540321
申请日：2006-09-29
申请人： Simon Dodd , S. Jonathan Wang , Dennis W. Tom , Frank R. Bryant , Terry E. McMahon , Richard Todd Miller , Gregory T. Hindman
发明人： Simon Dodd , S. Jonathan Wang , Dennis W. Tom , Frank R. Bryant , Terry E. McMahon , Richard Todd Miller , Gregory T. Hindman
IPC分类号： B41J2/05
CPC分类号： B41J2/1628 , B41J2/14129 , B41J2/1603 , B41J2202/13 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a semiconductor device, the method including forming a substrate including a first surface having a non-doped region, forming an insulative material over the first surface of the substrate, forming a first conductive material over the first insulative material, forming an opening in the first conductive material that forms a path to the substrate that is substantially free of the first conductive material and the first insulative material, forming a second insulative material over the first conductive material, and forming a second conductive material over the second insulative material, wherein the second conductive material is formed in the opening and contacts the non-doped region of the substrate.
摘要翻译： 一种形成半导体器件的方法，所述方法包括形成包括具有非掺杂区域的第一表面的衬底，在所述衬底的第一表面上形成绝缘材料，在所述第一绝缘材料上形成第一导电材料，形成第 在所述第一导电材料中开口，所述第一导电材料形成基本上不含所述第一导电材料和所述第一绝缘材料的路径，在所述第一导电材料上形成第二绝缘材料，以及在所述第二绝缘材料上形成第二导电材料 ，其中所述第二导电材料形成在所述开口中并接触所述衬底的非掺杂区域。
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公开(公告)号：US06534841B1
公开(公告)日：2003-03-18
申请号：US10017567
申请日：2001-12-14
申请人： Andrew L. Van Brocklin , Kenneth J. Eldredge , S. Jonathan Wang , Frederick A Perner , Peter Fricke
发明人： Andrew L. Van Brocklin , Kenneth J. Eldredge , S. Jonathan Wang , Frederick A Perner , Peter Fricke
IPC分类号： H01L2900
CPC分类号： H01L23/5252 , H01L27/10 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A memory structure has an antifuse material that is unpatterned and sandwiched between each of a plurality of antifuse electrode pairs. The antifuse material is continuous between the antifuse electrode pairs. Furthermore the present invention includes a memory structure comprising a plurality of antifuse electrode pairs forming a plurality of row conductors and a plurality of middle conductors in electrical communication with a plurality of control elements.
摘要翻译： 存储器结构具有未图案化并夹在多个反熔丝电极对中的每一个之间的反熔丝材料。 反熔丝材料在反熔丝电极对之间是连续的。 此外，本发明包括一种存储结构，该存储结构包括形成多个行导体的多个反熔丝电极对以及与多个控制元件电连通的多个中间导体。
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