公开(公告)号：US20240194578A1

公开(公告)日：2024-06-13

申请号：US18377442

申请日：2023-10-06

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Yejie HONG ,  Gao HUANG ,  Benxia HUANG ,  Wenjian LIN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49833

Abstract: An embedded device package substrate includes a line board including a first insulating layer and a first line layer located on an upper surface of the first insulating layer, a core layer covering the first line layer and including a preset opening, a device embedded in the preset opening, a packaging layer covering the core layer and filling the gap between the core layer and the device, and an outer line layer located on the packaging layer. The outer line layer is connected to a terminal of the device by a first conductive column penetrating through the packaging layer and to the first line layer by a second conductive column penetrating through the core layer and the packaging layer.

公开(公告)号：US20240153819A1

公开(公告)日：2024-05-09

申请号：US18454022

申请日：2023-08-22

Applicant: Zhuhai ACCESS Semiconductor Co., LTD.

Inventor： Xianming CHEN ,  Gao HUANG ,  Wenjian LIN ,  Yejie HONG ,  Benxia HUANG ,  Juchen HUANG

IPC: H01L21/768 ,  H01L21/48 ,  H01L23/13 ,  H01L23/14

CPC classification number: H01L21/76885 ,  H01L21/4828 ,  H01L23/13 ,  H01L23/14

Abstract: A substrate manufacturing method, an embedded substrate and a semiconductor are disclosed. The method includes: manufacturing a first semi-finished substrate including first circuit layers and a first dielectric layer arranged in staggered and laminated manner; arranging a viscous material layer on the first circuit layer to form a device adhering area; adhering an embedded device on the device adhering area, a pin face of the embedded device facing away from the viscous material layer; laminating a second dielectric layer on the first circuit layer, which covers the viscous material layer and the embedded device; manufacturing a first conductive pillar, a second conductive pillar and a second circuit layer, the first conductive pillar extending through the second dielectric layer and configured for connecting the second circuit layer with the first circuit layer, the second conductive pillar being configured for connecting the embedded device with the second circuit layer.

公开(公告)号：US20240063055A1

公开(公告)日：2024-02-22

申请号：US18221004

申请日：2023-07-12

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Benxia HUANG ,  Lei FENG ,  Jindong FENG ,  Yejie HONG

IPC: H01L21/768 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/47

CPC classification number: H01L21/76805 ,  H01L21/76832 ,  H01L21/32139 ,  H01L21/0234 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/02645 ,  H01L21/47

Abstract: A method for manufacturing a device embedded packaging structure include laminating a first dielectric material on a copper foil to form a first dielectric layer, and forming a first feature pattern in the first dielectric layer to expose the copper foil, etching the exposed copper foil to form a device opening frame and a via post opening frame to obtain a metal frame, applying an adhesive layer on the metal frame, and mounting a device to the adhesive layer in the device opening frame, laminating a second dielectric material to form a second dielectric layer covering the metal frame and filling the device opening frame and the via post opening frame, forming a via post in the via post opening frame, and forming a first wiring layer and a second wiring layer conductively connected by the via post on the upper and lower surfaces of the second dielectric layer.

公开(公告)号：US20240021740A1

公开(公告)日：2024-01-18

申请号：US18220877

申请日：2023-07-12

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Lei FENG ,  Benxia HUANG ,  Jiangjiang ZHAO ,  Zhijun ZHANG

IPC: H01L31/0203 ,  H01L31/0232 ,  H01L31/024 ,  H01L31/12 ,  H01L31/18

CPC classification number: H01L31/0203 ,  H01L31/02325 ,  H01L31/024 ,  H01L31/125 ,  H01L31/18

Abstract: A method for manufacturing a light-emitting photosensitive sensor structure includes preparing a package substrate, wherein the package substrate has a cavity formed by a light-shield frame performing enclosing, and the bottom of the cavity is provided with a first line layer, forming a light transmission channel on the light-shield frame, mounting a light-emitting photosensitive sensor in the cavity of the package substrate so that the photosensitive luminescent device is electrically connected to the first line layer, filling the cavity and the light transmission channel with a transparent encapsulating material to form a transparent packaging layer on the photosensitive luminescent device, forming a light-shield layer on the transparent packaging layer, and performing cutting along a cutting line of the light-shield frame to obtain a light-emitting photosensitive sensor structure having a directional light transmission channel.

公开(公告)号：US20230092164A1

公开(公告)日：2023-03-23

申请号：US17945200

申请日：2022-09-15

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Lei FENG ,  Benxia HUANG ,  Yejie HONG

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/495

Abstract: A package substrate based on a molding process may include an encapsulation layer, a support frame located in the encapsulation layer, a base, a device located on an upper surface of the base, a copper boss located on a lower surface of the base, a conductive copper pillar layer penetrating the encapsulation layer in the height direction, and a first circuit layer and a second circuit layer over and under the encapsulation layer. The second circuit layer includes a second conductive circuit and a heat dissipation circuit, the first circuit layer and the second conductive circuit are connected conductively through the conductive copper pillar layer, the heat dissipation circuit is connected to one side of the device through the copper boss and the base, and the first circuit layer is connected to the other side of the device.

公开(公告)号：US20220285088A1

公开(公告)日：2022-09-08

申请号：US17683697

申请日：2022-03-01

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Wenshi WANG ,  Lei FENG ,  Benxia HUANG

IPC: H01F27/29 ,  H01F17/00 ,  H01F17/04 ,  H01F41/02

Abstract: An inductor-integrating embedded support frame according to an embodiment of the present disclosure includes a core dielectric layer, a through-opening penetrating through the core dielectric layer, wherein the through-opening is used for embedding and installing a device, and an inductor, wherein the inductor includes a magnetic core embedded in the core dielectric layer and an inductance coil wound around the magnetic core, wherein at least one conductive copper pillar penetrating through the core dielectric layer is provided at the periphery of the through-opening and the inductor.

公开(公告)号：US20210399400A1

公开(公告)日：2021-12-23

申请号：US17220151

申请日：2021-04-01

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Lei FENG ,  Benxia HUANG ,  Jindong FENG ,  Yejie HONG

IPC: H01P11/00

Abstract: A method for manufacturing an embedded package structure having an air resonant cavity according to an embodiment includes manufacturing a first substrate including a first insulating layer, a chip embedded in the insulating layer, and a wiring layer on a terminal face of the chip of the first substrate, wherein the wiring layer is provided thereon with an opening revealing the terminal face of the chip; manufacturing a second substrate which comprises a second insulating layer; locally applying a first adhesive layer on the wiring layer such that the opening revealing the terminal face of the chip is not covered; and applying a second adhesive layer on the second substrate; and attaching and curing the first adhesive layer of the first substrate and the second adhesive layer of the second substrate to obtain an embedded package structure having an air resonant cavity on the terminal face of the chip.

公开(公告)号：US20240222245A1

公开(公告)日：2024-07-04

申请号：US18455553

申请日：2023-08-24

Applicant: Zhuhai ACCESS Semiconductor Co., LTD.

Inventor： Xianming CHEN ,  Gao HUANG ,  Yejie HONG ,  Wenjian LIN ,  Benxia HUANG ,  Zhijun ZHANG

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/02 ,  H05K1/18

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H05K1/0298 ,  H05K1/182 ,  H05K2201/10242

Abstract: A method for manufacturing embedded device packaging substrate, a packaging substrate, and a semiconductor are disclosed. The method includes: forming a first circuit layer; laminating a first photosensitive layer onto the first circuit layer; providing an embedded device on the first photosensitive layer, with a pin face of the embedded device facing away from the first photosensitive layer; providing a second photosensitive layer covering the embedded device; partially removing the first dielectric layer such that a minimum thickness of the first dielectric layer covering a side surface of the embedded device is greater than or equal to a preset threshold; providing a second dielectric layer covering the first dielectric layer; and forming, on the second dielectric layer, a second circuit layer that is electrically connected to the first circuit layer and the embedded device.

公开(公告)号：US20240116752A1

公开(公告)日：2024-04-11

申请号：US18377419

申请日：2023-10-06

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Lei FENG ,  Jiangjiang ZHAO ,  Benxia HUANG ,  Gao HUANG ,  Yejie HONG

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00301 ,  B81B7/0061 ,  B81C1/00309 ,  B81B2207/092 ,  B81C2203/0118

Abstract: A packaged cavity structure includes an embedded packaging frame having a first cavity and a first conductive post respectively penetrating an insulation layer in a height direction, a chipset within the first cavity, a first circuit layer on an upper surface of the embedded packaging frame, a first dielectric layer on the first circuit layer, a second circuit layer on the first dielectric layer, a through-hole penetrating the first dielectric layer and the insulation layer, a third circuit layer on a lower surface of the embedded packaging frame, a support post enclosure on the third circuit layer, and a packaging layer formed along the outside of the support post enclosure. A second cavity communicating with the through-hole is formed between the packaging layer and the lower surface of the embedded packaging frame, and the chipset includes a first chip and a second chip provided in a back-to-back stack.

公开(公告)号：US20240071852A1

公开(公告)日：2024-02-29

申请号：US18221518

申请日：2023-07-13

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Wenjian LIN ,  Gao HUANG ,  Benxia HUANG

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/3121 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16225

Abstract: A manufacturing method for an embedded flip chip package substrate includes laminating a first dielectric layer on the first line layer formed on a carrier plate, forming a first window on the first dielectric layer, filling a first copper post in the first window, forming a second window on the first dielectric layer, mounting a flip chip to the second window, sequentially stacking a packaging layer and a second dielectric layer covered with a first metal layer on the first dielectric layer, pressing a packaging layer encapsulating the first copper post and the flip chip and a second dielectric layer, curing the packaging layer, opening a hole through the first metal layer, the second dielectric layer and the packaging layer to form an interlayer conducting blind hole, forming a second line layer on the first metal layer, and removing the carrier plate to obtain a package substrate.