PACKAGED CAVITY STRUCTURE AND MANUFACTURING METHOD THEREOF

    公开(公告)号:US20240116752A1

    公开(公告)日:2024-04-11

    申请号:US18377419

    申请日:2023-10-06

    IPC分类号: B81C1/00 B81B7/00

    摘要: A packaged cavity structure includes an embedded packaging frame having a first cavity and a first conductive post respectively penetrating an insulation layer in a height direction, a chipset within the first cavity, a first circuit layer on an upper surface of the embedded packaging frame, a first dielectric layer on the first circuit layer, a second circuit layer on the first dielectric layer, a through-hole penetrating the first dielectric layer and the insulation layer, a third circuit layer on a lower surface of the embedded packaging frame, a support post enclosure on the third circuit layer, and a packaging layer formed along the outside of the support post enclosure. A second cavity communicating with the through-hole is formed between the packaging layer and the lower surface of the embedded packaging frame, and the chipset includes a first chip and a second chip provided in a back-to-back stack.

    CAPACITOR AND INDUCTOR EMBEDDED STRUCTURE AND MANUFACTURING METHOD THEREFOR, AND SUBSTRATE

    公开(公告)号:US20230197739A1

    公开(公告)日:2023-06-22

    申请号:US17998159

    申请日:2020-07-24

    IPC分类号: H01L27/13

    CPC分类号: H01L27/13 H01L28/10 H01L28/40

    摘要: A capacitor and inductor embedded structure and a manufacturing method therefor, and a substrate are disclosed. The method includes: providing a metal plate; sequentially depositing and etching a first protective layer, a thin film dielectric layer, a second protective layer, and an upper electrode layer on an upper surface of the metal plate to form a thin film capacitor and a capacitor upper electrode; pressing an upper dielectric layer to the upper surface of the metal plate, covering the thin film capacitor and the capacitor upper electrode, and etching the metal plate to form a capacitor lower electrode; pressing a lower dielectric layer to a lower surface of the metal plate, and performing drilling on the upper dielectric layer and the lower dielectric layer to form inductor through holes and capacitor electrode through holes; electroplating metal to form an inductor and circuit layers.

    PACKAGE SUBSTRATE BASED ON MOLDING PROCESS AND MANUFACTURING METHOD THEREOF

    公开(公告)号:US20230092164A1

    公开(公告)日:2023-03-23

    申请号:US17945200

    申请日:2022-09-15

    摘要: A package substrate based on a molding process may include an encapsulation layer, a support frame located in the encapsulation layer, a base, a device located on an upper surface of the base, a copper boss located on a lower surface of the base, a conductive copper pillar layer penetrating the encapsulation layer in the height direction, and a first circuit layer and a second circuit layer over and under the encapsulation layer. The second circuit layer includes a second conductive circuit and a heat dissipation circuit, the first circuit layer and the second conductive circuit are connected conductively through the conductive copper pillar layer, the heat dissipation circuit is connected to one side of the device through the copper boss and the base, and the first circuit layer is connected to the other side of the device.