公开(公告)号：US20070001174A1

公开(公告)日：2007-01-04

申请号：US11169378

申请日：2005-06-29

申请人： Zoltan Ring ,  Helmut Hagleitner ,  Jason Henning ,  Andrew Mackenzie ,  Scott Allen ,  Scott Sheppard ,  Richard Smith ,  Saptharishi Sriram ,  Allan Ward

发明人： Zoltan Ring ,  Helmut Hagleitner ,  Jason Henning ,  Andrew Mackenzie ,  Scott Allen ,  Scott Sheppard ,  Richard Smith ,  Saptharishi Sriram ,  Allan Ward

IPC分类号： H01L29/15 ,  H01L31/0256

CPC分类号： H01L21/045 ,  H01L21/3145 ,  H01L21/318 ,  H01L21/3185 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/24

摘要： A passivated semiconductor structure and associated method are disclosed. The structure includes a silicon carbide substrate or layer; an oxidation layer on the silicon carbide substrate for lowering the interface density between the silicon carbide substrate and the thermal oxidation layer; a first sputtered non-stoichiometric silicon nitride layer on the thermal oxidation layer for reducing parasitic capacitance and minimizing device trapping; a second sputtered non-stoichiometric silicon nitride layer on the first layer for positioning subsequent passivation layers further from the substrate without encapsulating the structure; a sputtered stoichiometric silicon nitride layer on the second sputtered layer for encapsulating the structure and for enhancing the hydrogen barrier properties of the passivation layers; and a chemical vapor deposited environmental barrier layer of stoichiometric silicon nitride for step coverage and crack prevention on the encapsulant layer.

摘要翻译： 公开了钝化的半导体结构和相关方法。 该结构包括碳化硅衬底或层; 在碳化硅衬底上的氧化层，用于降低碳化硅衬底和热氧化层之间的界面密度; 在热氧化层上的第一溅射的非化学计量的氮化硅层，用于减少寄生电容并最小化器件捕获; 在所述第一层上的第二溅射的非化学计量的氮化硅层，用于使所述衬底进一步从所述衬底定位以后的钝化层而不封装所述结构; 在第二溅射层上溅射化学计量的氮化硅层，用于封装该结构并增强钝化层的氢阻挡性能; 以及化学气相沉积的化学计量氮化硅的环境阻挡层，用于在封装层上进行步骤覆盖和防裂。

公开(公告)号：US20070018199A1

公开(公告)日：2007-01-25

申请号：US11185398

申请日：2005-07-20

申请人： Scott Sheppard ,  Andrew Mackenzie ,  Scott Allen ,  Richard Smith

发明人： Scott Sheppard ,  Andrew Mackenzie ,  Scott Allen ,  Richard Smith

IPC分类号： H01L31/00

CPC分类号： H01L29/66431 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L29/802 ,  H01L2924/13064

摘要： A III-Nitride field-effect transistor, specifically a HEMT, comprises a channel layer, a barrier layer on the channel layer, an etch stop layer on the cap layer, a dielectric layer on the etch stop layer, a gate recess that extends to the barrier layer, and a gate contact in the gate recess. The etch stop layer may reduce damage associated with forming the recessed gate by not exposing the barrier layer to dry etching. The etch stop layer in the recess is removed and the remaining etch stop layer serves as a passivation layer.

摘要翻译： III型氮化物场效应晶体管，特别是HEMT，包括沟道层，沟道层上的势垒层，覆盖层上的蚀刻停止层，蚀刻停止层上的介电层，延伸到 阻挡层和栅极接触。 蚀刻停止层可以通过不将阻挡层暴露于干蚀刻来减少与形成凹陷栅的相关的损伤。 去除凹槽中的蚀刻停止层，剩余的蚀刻停止层用作钝化层。

公开(公告)号：US20080035934A1

公开(公告)日：2008-02-14

申请号：US11845805

申请日：2007-08-28

申请人： Scott Sheppard ,  Richard Smith ,  Zoltan Ring

发明人： Scott Sheppard ,  Richard Smith ,  Zoltan Ring

IPC分类号： H01L29/15

CPC分类号： H01L29/66462 ,  H01L21/045 ,  H01L21/3145 ,  H01L21/318 ,  H01L21/3185 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/7787

摘要： An improved field effect transistor formed in the Group III nitride material system includes a two part structure in which a chemical vapor deposited passivation layer of silicon nitride encapsulates a previously sputtered-deposited layer of silicon nitride. The sputtered layer provides some of the benefits of passivation and the chemical vapor deposited layer provides an excellent environmental barrier.

摘要翻译： 形成在III族氮化物材料体系中的改进的场效应晶体管包括二部分结构，其中氮化硅的化学气相沉积钝化层封装预先溅射的氮化硅层。 溅射层提供了钝化的一些优点，并且化学气相沉积层提供了优异的环境屏障。

公开(公告)号：US20060255366A1

公开(公告)日：2006-11-16

申请号：US11358241

申请日：2006-02-21

申请人： Scott Sheppard ,  Richard Smith ,  Zoltan Ring

发明人： Scott Sheppard ,  Richard Smith ,  Zoltan Ring

IPC分类号： H01L29/739

CPC分类号： H01L29/66462 ,  H01L29/2003 ,  H01L29/7783

摘要： Transistors are fabricated by forming a nitride-based semiconductor barrier layer on a nitride-based semiconductor channel layer and forming a protective layer on a gate region of the nitride-based semiconductor barrier layer. Patterned ohmic contact metal regions are formed on the barrier layer and annealed to provide first and second ohmic contacts. The annealing is carried out with the protective layer on the gate region. A gate contact is also formed on the gate region of the barrier layer. Transistors having protective layer in the gate region are also provided as are transistors having a barrier layer with a sheet resistance substantially the same as an as-grown sheet resistance of the barrier layer.

摘要翻译： 晶体管通过在氮化物基半导体沟道层上形成氮化物基半导体势垒层并在氮化物基半导体势垒层的栅极区上形成保护层来制造晶体管。 图案化的欧姆接触金属区形成在阻挡层上并退火以提供第一和第二欧姆接触。 退火是在栅极区域上的保护层进行的。 栅极接触也形成在阻挡层的栅极区上。 还提供了在栅极区域中具有保护层的晶体管，就像具有阻挡层的晶体管一样，薄膜电阻基本上与阻挡层的片状电阻基本相同。

公开(公告)号：US20050170574A1

公开(公告)日：2005-08-04

申请号：US10758871

申请日：2004-01-16

申请人： Scott Sheppard ,  Richard Smith ,  Zoltan Ring

发明人： Scott Sheppard ,  Richard Smith ,  Zoltan Ring

IPC分类号： H01L21/335 ,  H01L29/20 ,  H01L29/778 ,  H01L21/338

CPC分类号： H01L29/66462 ,  H01L29/2003 ,  H01L29/7783

摘要： Transistors are fabricated by forming a nitride-based semiconductor barrier layer on a nitride-based semiconductor channel layer and forming a protective layer on a gate region of the nitride-based semiconductor barrier layer. Patterned ohmic contact metal regions are formed on the barrier layer and annealed to provide first and second ohmic contacts. The annealing is carried out with the protective layer on the gate region. A gate contact is also formed on the gate region of the barrier layer. Transistors having protective layer in the gate region are also provided as are transistors having a barrier layer with a sheet resistance substantially the same as an as-grown sheet resistance of the barrier layer.

摘要翻译： 晶体管通过在氮化物基半导体沟道层上形成氮化物基半导体势垒层并在氮化物基半导体势垒层的栅极区上形成保护层来制造晶体管。 图案化的欧姆接触金属区形成在阻挡层上并退火以提供第一和第二欧姆接触。 退火是在栅极区域上的保护层进行的。 栅极接触也形成在阻挡层的栅极区上。 还提供了在栅极区域中具有保护层的晶体管，就像具有阻挡层的晶体管一样，薄膜电阻基本上与阻挡层的片状电阻基本相同。

公开(公告)号：US20060226412A1

公开(公告)日：2006-10-12

申请号：US11103117

申请日：2005-04-11

申请人： Adam Saxler ,  Yifeng Wu ,  Primit Parikh ,  Umesh Mishra ,  Richard Smith ,  Scott Sheppard

发明人： Adam Saxler ,  Yifeng Wu ,  Primit Parikh ,  Umesh Mishra ,  Richard Smith ,  Scott Sheppard

IPC分类号： H01L29/06

CPC分类号： H01L21/0254 ,  H01L21/0237 ,  H01L21/02425 ,  H01L21/02439 ,  H01L21/02491 ,  H01L21/02581 ,  H01L21/0262 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/66462 ,  H01L29/7787

摘要： Semiconductor device structures and methods of fabricating semiconductor devices structures are provided that include a semi-insulating or insulating GaN epitaxial layer on a conductive semiconductor substrate and/or a conductive layer. The semi-insulating or insulating GaN epitaxial layer has a thickness of at least about 4 μm. GaN semiconductor device structures and methods of fabricating GaN semiconductor device structures are also provided that include an electrically conductive SiC substrate and an insulating or semi-insulating GaN epitaxial layer on the conductive SiC substrate. The GaN epitaxial layer has a thickness of at least about 4 μm. GaN semiconductor device structures and methods of fabricating GaN semiconductor device structures are also provided that include an electrically conductive GaN substrate, an insulating or semi-insulating GaN epitaxial layer on the conductive GaN substrate, a GaN based semiconductor device on the GaN epitaxial layer and a via hole and corresponding via metal in the via hole that extends through layers of the GaN based semiconductor device and the GaN epitaxial layer.

摘要翻译： 提供半导体器件结构和制造半导体器件结构的方法，其包括在导电半导体衬底和/或导电层上的半绝缘或绝缘GaN外延层。 半绝缘或绝缘GaN外延层具有至少约4μm的厚度。 还提供GaN半导体器件结构和制造GaN半导体器件结构的方法，其包括在导电SiC衬底上的导电SiC衬底和绝缘或半绝缘GaN外延层。 GaN外延层具有至少约4μm的厚度。 还提供GaN半导体器件结构和制造GaN半导体器件结构的方法，其包括导电GaN衬底，导电GaN衬底上的绝缘或半绝缘GaN外延层，GaN外延层上的GaN基半导体器件和 通孔和通孔中相应的通孔金属延伸穿过GaN基半导体器件和GaN外延层的层。

公开(公告)号：US20060017064A1

公开(公告)日：2006-01-26

申请号：US10899215

申请日：2004-07-26

申请人： Adam Saxler ,  Scott Sheppard ,  Richard Smith

发明人： Adam Saxler ,  Scott Sheppard ,  Richard Smith

IPC分类号： H01L29/739

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/66462

摘要： High electron mobility transistors and/or methods of fabricating high electron mobility transistors that include a first Group III-nitride layer having vertically grown regions, laterally grown regions and a coalescence region are provided. A Group III-nitride channel layer is provided on the first Group III-nitride layer and a Group III-nitride barrier layer is provided on the Group III-nitride channel layer. A drain contact, a source contact and a gate contact are provided on the barrier layer. The gate contact is disposed on a portion of the barrier layer on a laterally grown region of the first Group III-nitride layer and at least a portion of one of the source contact and/or the drain contact is disposed on a portion of the barrier layer on a vertically grown region of the first Group III-nitride layer.

公开(公告)号：US20060019435A1

公开(公告)日：2006-01-26

申请号：US10897726

申请日：2004-07-23

申请人： Scott Sheppard ,  Richard Smith

发明人： Scott Sheppard ,  Richard Smith

IPC分类号： H01L21/338

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786 ,  H01L2924/13064

摘要： An anneal of a gate recess prior to formation of a gate contact, such as a Schottky contact, may reduce gate leakage and/or provide a high quality gate contact in a semiconductor device, such as a transistor. The use of an encapsulation layer during the anneal may further reduce damage to the semiconductor in the gate recess of the transistor. The anneal may be provided, for example, by an anneal of ohmic contacts of the device. Thus, high quality gate and ohmic contacts may be provided with reduced degradation of the gate region that may result from providing a recessed gate structure as a result of etch damage in forming the recess.

摘要翻译： 在形成诸如肖特基接触之类的栅极接触之前的栅极凹槽的退火可以减少栅极泄漏和/或在诸如晶体管的半导体器件中提供高质量的栅极接触。 在退火期间使用封装层可以进一步降低对晶体管的栅极凹槽中的半导体的损坏。 退火可以例如通过器件的欧姆接触的退火来提供。 因此，可以提供高质量的栅极和欧姆接触，由于在形成凹槽时由于蚀刻损伤而提供凹陷的栅极结构可能导致栅极区域的降低。

公开(公告)号：US20050258431A1

公开(公告)日：2005-11-24

申请号：US10851507

申请日：2004-05-22

申请人： Richard Smith ,  Scott Sheppard ,  John Palmour

发明人： Richard Smith ,  Scott Sheppard ,  John Palmour

IPC分类号： H01L21/314 ,  H01L21/316 ,  H01L21/335 ,  H01L23/31 ,  H01L29/20 ,  H01L29/778 ,  H01L31/108 ,  H01L27/15

CPC分类号： H01L29/7787 ,  H01L23/3192 ,  H01L29/2003 ,  H01L29/66462 ,  H01L31/1085 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is disclosed that includes a layer of Group III nitride semiconductor material that includes at least one surface, a control contact on the surface for controlling the electrical response of the semiconductor material, a dielectric barrier layer covering at least a portion of the one surface adjacent the control contact, the dielectric barrier layer having a bandgap greater than the bandgap of the Group III nitride and a conduction band offset from the conduction band of the Group III nitride; and a dielectric protective layer covering the remainder of the Group III nitride surface.

摘要翻译： 公开了一种半导体器件，其包括III族氮化物半导体材料层，其包括至少一个表面，用于控制半导体材料的电响应的表面上的控制触点，覆盖该半导体材料的至少一部分的电介质阻挡层 表面邻近控制触点，电介质阻挡层的带隙大于III族氮化物的带隙，导带偏离第III族氮化物的导带; 以及覆盖III族氮化物表面的其余部分的介电保护层。

公开(公告)号：US20070254418A1

公开(公告)日：2007-11-01

申请号：US11810026

申请日：2007-06-04

申请人： Scott Sheppard ,  Richard Smith

发明人： Scott Sheppard ,  Richard Smith

IPC分类号： H01L29/778

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786 ,  H01L2924/13064

摘要： An anneal of a gate recess prior to formation of a gate contact, such as a Schottky contact, may reduce gate leakage and/or provide a high quality gate contact in a semiconductor device, such as a transistor. The use of an encapsulation layer during the anneal may further reduce damage to the semiconductor in the gate recess of the transistor. The anneal may be provided, for example, by an anneal of ohmic contacts of the device. Thus, high quality gate and ohmic contacts may be provided with reduced degradation of the gate region that may result from providing a recessed gate structure as a result of etch damage in forming the recess.