公开(公告)号：US10374114B2

公开(公告)日：2019-08-06

申请号：US14777484

申请日：2014-03-11

Applicant: ams AG

Inventor： Jordi Teva ,  Frederic Roger ,  Ewald Stueckler ,  Stefan Jessenig ,  Rainer Minixhofer ,  Ewald Wachmann ,  Martin Schrems ,  Guenther Koppitsch

IPC: H01L31/107 ,  H01L31/0224 ,  H01L31/0352 ,  H01L31/0368 ,  H01L31/18

Abstract: The lateral single-photon avalanche diode comprises a semiconductor body comprising a semiconductor material of a first type of electric conductivity, a trench in the semiconductor body, and anode and cathode terminals. A junction region of the first type of electric conductivity is located near the sidewall of the trench, and the electric conductivity is higher in the junction region than at a farther distance from the sidewall. A semiconductor layer of an opposite second type of electric conductivity is arranged at the sidewall of the trench adjacent to the junction region. The anode and cathode terminals are electrically connected with the semiconductor layer and with the junction region, respectively. The junction region may be formed by a sidewall implantation.

公开(公告)号：US10062610B2

公开(公告)日：2018-08-28

申请号：US15520821

申请日：2015-10-15

Applicant: ams AG

Inventor： Guenther Koppitsch ,  Bernhard Loeffler

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/48 ,  H01L21/3065

CPC classification number: H01L21/76898 ,  H01L21/3065 ,  H01L21/30655 ,  H01L23/481

Abstract: An opening (17) is etched from a main surface (10) of a substrate (1) of semiconductor material by deep reactive ion etching comprising a plurality of cycles, each of the cycles including a deposition of a passivation in the opening and an application of an etchant. An additional etching is performed between two consecutive cycles by an application of a further etchant that is different from the etchant. The passivation layer (9) is thus etched above a sidewall (7) of the opening to remove undesired protrusions.

公开(公告)号：US09466529B2

公开(公告)日：2016-10-11

申请号：US14766412

申请日：2014-01-29

Applicant: ams AG

Inventor： Guenther Koppitsch ,  Ewald Stueckler ,  Karl Rohracher ,  Jordi Teva

IPC: H01L21/76 ,  H01L21/768 ,  G03F7/09 ,  H01L21/033

CPC classification number: H01L21/76882 ,  G03F7/094 ,  H01L21/0335 ,  H01L21/7685 ,  H01L21/76883 ,  H01L21/76898

Abstract: The method comprises the steps of providing a semiconductor body or substrate (1) with a recess or trench (2) in a main surface (10), applying a mask (3) on the main surface, the mask covering the recess or trench, so that the walls and bottom of the recess or trench and the mask together enclose a cavity (4), which is filled with a gas, and forming at least one opening (5) in the mask at a distance from the recess or trench, the distance (6) being adapted to allow the gas to escape from the cavity via the opening when the gas pressure exceeds an external pressure.

Abstract translation: 该方法包括以下步骤：在主表面（10）中提供具有凹槽或沟槽（2）的半导体本体或衬底（1），在主表面上施加掩模（3），覆盖凹部或沟槽的掩模， 使得凹部或沟槽和面罩的壁和底部一起包围填充有气体的空腔（4），并且在距离凹部或沟槽一定距离处的掩模中形成至少一个开口（5） 所述距离（6）适于当所述气体压力超过外部压力时允许所述气体经由所述开口从所述空腔逸出。