公开(公告)号：US09870988B2

公开(公告)日：2018-01-16

申请号：US15691654

申请日：2017-08-30

Applicant: ams AG

Inventor： Cathal Cassidy ,  Martin Schrems ,  Franz Schrank

IPC: H01L21/44 ,  H01L23/522 ,  H01L23/00 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L23/552

CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/53295 ,  H01L23/552 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/10125 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13561 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16106 ,  H01L2224/1613 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/30101 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A semiconductor substrate is provided with an annular cavity extending from a front side of the substrate to an opposite rear side. A metallization is applied in the annular cavity, thereby forming a through-substrate via and leaving an opening of the annular cavity at the front side. A solder ball is placed above the opening and a reflow of the solder ball is effected, thereby forming a void of the through-substrate via, the void being covered by the solder ball.

公开(公告)号：US11411035B2

公开(公告)日：2022-08-09

申请号：US16309226

申请日：2017-06-13

Applicant: ams AG

Inventor： Martin Schrems ,  Thomas Stockmeier

IPC: H01L27/146 ,  G02B5/20

Abstract: The system-on-chip camera comprises a semiconductor body (1) with an integrated circuit (40), a sensor substrate (2), sensor elements (3) arranged in the sensor substrate according to an array of pixels, a light sensor (4) in the sensor substrate apart from the sensor elements, and a lens or an array of lenses (15) on a surface of incidence (30). Filter elements (11, 12, 13), which may especially be interference filters for red, green or blue, are arranged between the sensor elements and the surface of incidence.

公开(公告)号：US11271134B2

公开(公告)日：2022-03-08

申请号：US16756025

申请日：2018-10-15

Applicant: ams AG

Inventor： Gregor Toschkoff ,  Thomas Bodner ,  Franz Schrank ,  Miklos Labodi ,  Joerg Siegert ,  Martin Schrems

IPC: H01L31/18 ,  H01L27/146 ,  G01J1/02 ,  G01J1/04 ,  H01L31/02 ,  H01L31/0203 ,  H01L31/0216

Abstract: A method for manufacturing an optical sensor is provided. The method comprises providing an optical sensor arrangement which comprises at least two optical sensor elements on a carrier, where the optical sensor arrangement comprises a light entrance surface at the side of the optical sensor elements facing away from the carrier. The method further comprises forming a trench between two optical sensor elements in a vertical direction which is perpendicular to the main plane of extension of the carrier, where the trench extends from the light entrance surface of the sensor arrangement at least to the carrier. Moreover, the method comprises coating the trench with an opaque material, forming electrical contacts for the at least two optical sensor elements on a back side of the carrier facing away from the optical sensor elements, and forming at least one optical sensor by dicing the optical sensor arrangement along the trench. Each optical sensor comprises an optical sensor element, and the light entrance surface is free of electrical contacts and at least partially free of the opaque material above the optical sensor elements. Furthermore, an optical sensor is provided.

公开(公告)号：US09773729B2

公开(公告)日：2017-09-26

申请号：US15283189

申请日：2016-09-30

Applicant: ams AG

Inventor： Cathal Cassidy ,  Martin Schrems ,  Franz Schrank

IPC: H01L21/44 ,  H01L23/522 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L23/528 ,  H01L23/532 ,  H01L23/552 ,  H01L25/065

CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/53295 ,  H01L23/552 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/10125 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13561 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16106 ,  H01L2224/1613 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/30101 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A semiconductor substrate is provided with a through-substrate via comprising a metallization and an opening. A solder ball is placed on the opening. A reflow of the solder ball is performed in such a way that the solder ball closes the through-substrate via and leaves a void in the through-substrate via.

公开(公告)号：US09570390B2

公开(公告)日：2017-02-14

申请号：US14651197

申请日：2013-12-05

Applicant: ams AG

Inventor： Franz Schrank ,  Martin Schrems

IPC: H01L23/34 ,  H01L23/64 ,  H01L31/024 ,  H01L27/06 ,  H01L23/528 ,  G01N27/14 ,  H01L23/522 ,  G01N27/12 ,  G01N33/00

CPC classification number: H01L23/528 ,  G01N27/128 ,  G01N27/14 ,  G01N33/0004 ,  G01N33/0016 ,  H01L21/76898 ,  H01L23/345 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/647 ,  H01L27/0629 ,  H01L31/024 ,  H01L2223/6672 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device comprises a substrate of semiconductor material, a dielectric layer on the substrate, an electrically conductive contact pad arranged in the dielectric layer, a hot plate arranged in the dielectric layer, a recess of the substrate at the location of the hot plate, and an integrated circuit, which operates the hot plate. An electrically conductive layer is arranged on a side of the substrate opposite the dielectric layer. The substrate is provided with a via hole above the contact pad, and an electrically conductive material connecting the electrically conductive layer with the contact pad is applied in the via hole. The recess and the via hole are formed in the same process step.

Abstract translation: 半导体器件包括半导体材料的衬底，衬底上的电介质层，布置在电介质层中的导电接触焊盘，布置在电介质层中的热板，在热板的位置处的衬底的凹部， 以及操作热板的集成电路。 导电层布置在与电介质层相对的衬底的一侧上。 衬底在接触焊盘上方设置有通孔，并且将导电层与接触焊盘连接的导电材料施加在通孔中。 凹槽和通孔在相同的工艺步骤中形成。

公开(公告)号：US09553039B2

公开(公告)日：2017-01-24

申请号：US14359568

申请日：2012-11-07

Applicant: ams AG

Inventor： Cathal Cassidy ,  Martin Schrems ,  Franz Schrank

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/00 ,  H01L23/552 ,  H01L25/065

CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/53295 ,  H01L23/552 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/10125 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13561 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16106 ,  H01L2224/1613 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/30101 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: The semiconductor device comprises a semiconductor substrate (10) with a metallization (111) having an upper terminal layer (22) located at a front side (20) of the substrate. The metallization forms a through-substrate via (23) from the upper terminal layer to a rear terminal layer (13) located opposite to the front side at a rear side (21) of the substrate. The through-substrate via comprises a void (101), which may be filled with air or another gas. A solder ball (100) closes the void without completely filling it. A variety of interconnections for three dimensional integration is offered by this scheme.

Abstract translation: 半导体器件包括具有金属化（111）的半导体衬底（10），其具有位于衬底的前侧（20）的上端子层（22）。 金属化从基板的后侧（21）形成从上端子层到后端子层（13）的通孔（23）。 贯通基板通孔包括空隙（101），其可以填充有空气或另一种气体。 焊球（100）在不完全填充的情况下关闭空隙。 该方案提供了用于三维集成的各种互连。

公开(公告)号：US20140339698A1

公开(公告)日：2014-11-20

申请号：US14359568

申请日：2012-11-07

Applicant: ams AG

Inventor： Cathal Cassidy ,  Martin Schrems ,  Franz Schrank

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/53295 ,  H01L23/552 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/10125 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13561 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16106 ,  H01L2224/1613 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/30101 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: The semiconductor device comprises a semiconductor substrate (10) with a metallization (111) having an upper terminal layer (22) located at a front side (20) of the substrate. The metallization forms a through-substrate via (23) from the upper terminal layer to a rear terminal layer (13) located opposite to the front side at a rear side (21) of the substrate. The through-substrate via comprises a void (101), which may be filled with air or another gas. A solder ball (100) closes the void without completely filling it. A variety of interconnections for three dimensional integration is offered by this scheme.

Abstract translation: 半导体器件包括具有金属化（111）的半导体衬底（10），其具有位于衬底的前侧（20）的上端子层（22）。 金属化从基板的后侧（21）形成从上端子层到后端子层（13）的通孔（23）。 贯通基板通孔包括空隙（101），其可以填充有空气或另一种气体。 焊球（100）在不完全填充的情况下关闭空隙。 该方案提供了用于三维集成的各种互连。

公开(公告)号：US10340254B2

公开(公告)日：2019-07-02

申请号：US15726905

申请日：2017-10-06

Applicant: ams AG

Inventor： Jochen Kraft ,  Martin Schrems ,  Franz Schrank

IPC: H01L21/00 ,  H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L23/498 ,  H01L21/683 ,  H01L21/56 ,  H01L21/48 ,  H01L23/14 ,  H01L23/538

Abstract: The method of producing an interposer-chip-arrangement, comprises providing an interposer (1) with an integrated circuit (25), arranging a dielectric layer (2) with metal layers embedded in the dielectric layer above a main surface (10) of the interposer, connecting the integrated circuit with at least one of the metal layers, forming an interconnection (7) through the interposer, the interconnection contacting one of the metal layers, arranging a further dielectric layer (3) above a further main surface (11) of the interposer opposite the main surface and arranging a further metal layer in or on the further dielectric layer, the further metal layer being connected with the interconnection, arranging a chip provided with at least one contact pad at the main surface or at the further main surface, and electrically conductively connecting the contact pad with the interconnection.

公开(公告)号：US10283541B2

公开(公告)日：2019-05-07

申请号：US15528089

申请日：2015-11-09

Applicant: ams AG

Inventor： Joerg Siegert ,  Franz Schrank ,  Martin Schrems

IPC: H01L27/146 ,  H01L23/48

Abstract: A photosensor (2) is arranged in a semiconductor substrate (1) at a main surface (10), a dielectric layer (4) is arranged on or above the main surface, the dielectric layer including a metal layer (6) electrically connected with the photosensor, and an aperture layer (16) formed from an opaque or semitransparent material is arranged on or above the dielectric layer. The aperture layer is provided with an array of transparent aperture zones (18) above the photosensor, each of the aperture zones penetrating the aperture layer.

公开(公告)号：US09768131B2

公开(公告)日：2017-09-19

申请号：US15117175

申请日：2015-01-14

Applicant: ams AG

Inventor： Jochen Kraft ,  Karl Rohracher ,  Martin Schrems

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/00 ,  G01N27/12 ,  H01L23/48

CPC classification number: H01L24/02 ,  G01N27/12 ,  G01N27/128 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02315 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/114 ,  H01L2224/1148 ,  H01L2224/1161 ,  H01L2224/11616 ,  H01L2224/13013 ,  H01L2224/13022 ,  H01L2224/13026 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A wiring (3) comprising electrical conductors (4, 5, 6, 7) is formed in a dielectric layer (2) on or above a semiconductor substrate (1), an opening is formed in the dielectric layer to uncover a contact pad (8), which is formed by one of the conductors, and a further opening is formed in the dielectric layer to uncover an area of a further conductor (5), separate from the contact pad. The further opening is filled with an electrically conductive material (9), and the dielectric layer is thinned from a side opposite the substrate, so that the electrically conductive material protrudes from the dielectric layer.