公开(公告)号：US20240333289A1

公开(公告)日：2024-10-03

申请号：US18193861

申请日：2023-03-31

Applicant: intel Corporation

Inventor： Minki Cho ,  Balkaran Gill

IPC: H03K19/003 ,  H01L27/02

CPC classification number: H03K19/00315 ,  H01L27/0207

Abstract: The disclosure is directed to methods, a standard cell, and a system for forming a logic gate with reduced aging including organizing a plurality of transistors to provide a logic function for the logic gate, identifying a least one transistor in the plurality of transistors having a voltage swing to an output above a predetermined threshold, and coupling a voltage dividing transistor to the at least one transistor to reduce a voltage across the at least one transistor such that the voltage dividing transistor lowers a voltage across the at least one transistor.

公开(公告)号：US10114981B2

公开(公告)日：2018-10-30

申请号：US15396561

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Robert F. Kwasnick ,  Suraj Sindia ,  Clark N. Vandam ,  Balkaran Gill

IPC: G06F21/70 ,  G06N3/02 ,  H04Q9/00 ,  H04L12/28 ,  H04L12/26 ,  H04L29/08

Abstract: Apparatus, method, and system for remotely affecting the functionality and lifetime of an integrated circuit are described herein. One embodiment of a method includes: tracking a plurality of operational metrics relating to a monitored device, sending one or more of the plurality of operational metrics to a remote monitor and responsively receiving a command generated by the remote monitor, generating a threat level based on the plurality of operational metrics and the command, and performing a derating action based on the threat level. The command from the remote monitor may be generated by the remote monitor based, at least in part, on the one or more of the plurality of operational metrics. Alternatively, the command may be generated based on information obtained independently by the remote monitor and not based on the one or more of the plurality of operational metrics.

公开(公告)号：US20210391703A1

公开(公告)日：2021-12-16

申请号：US17125824

申请日：2020-12-17

Applicant: Intel Corporation

Inventor： Raj Singh Dua ,  Sanjay Joshi ,  Harry Muljono ,  Balkaran Gill

IPC: H02H3/08

Abstract: Analog Front End (AFE) driver or transmitter is used for ESD protection of an input-output (IO) pin, thus reducing ESD diode count and subsequently lowering the pad capacitance to achieve high performance in IO circuits like double data rate (DDR) IO, PCI Express (Peripheral Component Interconnect Express), etc. The channel of active devices that constitute AFE driver are used to connect an IO pad to discharge the ESD current to ground, thus providing an alternative path to ESD current and subsequently reducing the ESD diode count. An additional p-type device (Driver Path Enabler (DPE)) is coupled between the IO pad and a gate terminal of the AFE driver. This additional p-type device triggers the channel of the AFE driver. This p-type device is controlled by an RC based structure which cuts the p-type device off during regular operations when power is ramped-up.

公开(公告)号：US20240235545A9

公开(公告)日：2024-07-11

申请号：US17971619

申请日：2022-10-23

Applicant: Intel Corporation

Inventor： Minki Cho ,  Balkaran Gill ,  Anisur Rahman ,  Ketul B. Sutaria

IPC: H03K17/14 ,  G06F1/08

CPC classification number: H03K17/14 ,  G06F1/08 ,  H03K2217/94031

Abstract: This disclosure describes systems, methods, and devices related to clock gating. A device may detect that gating of a local clock of a computer core is enabled; detect, based on the detection that the gating is enabled, that a clock gating condition for the local clock is satisfied; and set a clock gating polarity of the local clock based on the detection that the clock gating condition for the local clock is satisfied.

公开(公告)号：US20240137016A1

公开(公告)日：2024-04-25

申请号：US17971619

申请日：2022-10-22

Applicant: Intel Corporation

Inventor： Minki Cho ,  Balkaran Gill ,  Anisur Rahman ,  Ketul B. Sutaria

IPC: H03K17/14 ,  G06F1/08

CPC classification number: H03K17/14 ,  G06F1/08 ,  H03K2217/94031

Abstract: This disclosure describes systems, methods, and devices related to clock gating. A device may detect that gating of a local clock of a computer core is enabled; detect, based on the detection that the gating is enabled, that a clock gating condition for the local clock is satisfied; and set a clock gating polarity of the local clock based on the detection that the clock gating condition for the local clock is satisfied.

公开(公告)号：US10078544B2

公开(公告)日：2018-09-18

申请号：US14975751

申请日：2015-12-19

Applicant: Intel Corporation

Inventor： Clark N. Vandam ,  Balkaran Gill ,  Junho Song ,  Suriya Suriya Ashok Kumar ,  Kasyap Pasumarthi

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/22 ,  G06F11/24 ,  G06F11/27

CPC classification number: G06F11/0793 ,  G06F11/0721 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/2236 ,  G06F11/24 ,  G06F11/27

Abstract: An apparatus and method are described for an on-chip reliability controller. For example, one embodiment of a processor comprises: a set of one or more cores to execute instructions and process data; a reliability controller to perform one or more self-test/diagnostic operations, the reliability controller to aggregate reliability data resulting from the self-test/diagnostic operations; a reliability estimator integral to the reliability controller to use the aggregated reliability data to perform a probability analysis to determine reliability estimates for one or more components of the processor; and a control unit integral to the reliability controller to adjust one or more variables and/or circuitry related to operation of the processor responsive to the reliability estimates.

公开(公告)号：US11662376B2

公开(公告)日：2023-05-30

申请号：US17705765

申请日：2022-03-28

Applicant: Intel Corporation

Inventor： Ketul B. Sutaria ,  Balkaran Gill

IPC: G01R31/28

CPC classification number: G01R31/2856 ,  G01R31/2874 ,  G01R31/2879

Abstract: An on-die early lifetime failure detection system with a reliability mechanism isolation circuit provides an early lifetime failure detection. The system measures and monitors reliability at time-0 (t0) and end-of-life. The measurements enable detection of latent reliability or marginality issues during the lifetime of the product. The system includes: a stress controller to adjust voltage for a power supply and voltage for a ground supply in accordance with one or more sensors; and an aging detector circuitry coupled to the stress controller, wherein the aging detector circuitry comprises a ring oscillator having delay stages, wherein each delay stage comprises an aging monitor circuitry, wherein the stress controller to adjust voltage for a power supply and voltage for a ground supply of the delay stage.

公开(公告)号：US20220368122A1

公开(公告)日：2022-11-17

申请号：US17876351

申请日：2022-07-28

Applicant: Intel Corporation

Inventor： Raj Singh Dua ,  Sanjay Joshi ,  Harry Muljono ,  Balkaran Gill

IPC: H02H3/08

Abstract: Analog Front End (AFE) driver or transmitter is used for ESD protection of an input-output (IO) pin, thus reducing ESD diode count and subsequently lowering the pad capacitance to achieve high performance in IO circuits like double data rate (DDR) TO, PCI Express (Peripheral Component Interconnect Express), etc. The channel of active devices that constitute AFE driver are used to connect an IO pad to discharge the ESD current to ground, thus providing an alternative path to ESD current and subsequently reducing the ESD diode count. An additional p-type device (Driver Path Enabler (DPE)) is coupled between the IO pad and a gate terminal of the AFE driver. This additional p-type device triggers the channel of the AFE driver. This p-type device is controlled by an RC based structure which cuts the p-type device off during regular operations when power is ramped-up.

公开(公告)号：US11287467B2

公开(公告)日：2022-03-29

申请号：US16844895

申请日：2020-04-09

Applicant: Intel Corporation

Inventor： Ketul B. Sutaria ,  Balkaran Gill

IPC: G01R31/28

Abstract: An on-die early lifetime failure detection system with a reliability mechanism isolation circuit provides an early lifetime failure detection. The system measures and monitors reliability at time-0 (t0) and end-of-life. The measurements enable detection of latent reliability or marginality issues during the lifetime of the product. The system includes: a stress controller to adjust voltage for a power supply and voltage for a ground supply in accordance with one or more sensors; and an aging detector circuitry coupled to the stress controller, wherein the aging detector circuitry comprises a ring oscillator having delay stages, wherein each delay stage comprises an aging monitor circuitry, wherein the stress controller to adjust voltage for a power supply and voltage for a ground supply of the delay stage.

公开(公告)号：US10803400B2

公开(公告)日：2020-10-13

申请号：US15191469

申请日：2016-06-23

Applicant: Intel Corporation

Inventor： Suraj Sindia ,  Lital Shiryan ,  Tamir Damian Munafo ,  Santosh Ghosh ,  Balkaran Gill

IPC: G06F21/32 ,  H04L29/06 ,  G06N20/00 ,  G06N3/08 ,  H04W12/00

Abstract: A self-adaptive security framework for a device is disclosed. A first security level for a device is set wherein the first security level comprises procedures that authenticate a user and allow the user to access the device. Input from sensors associated with the device may be received at a contextual sensing engine, wherein the input at least includes location data, and wherein at least a portion of the input is related to a physical setting where the device is located. A threat level for the device is determined in the physical setting via the contextual sensing engine based on analyzing the input. The first security level is altered to a second security level to provide an altered threat response for the device based on the threat level wherein the second security level has different procedures to authenticate the user compared to the first security level.