公开(公告)号：US20210288207A1

公开(公告)日：2021-09-16

申请号：US17202023

申请日：2021-03-15

Applicant: 1366 TECHNOLOGIES INC.

Inventor： Ralf JONCZYK ,  Patrick MCMAHON

IPC: H01L31/18

Abstract: A method includes etching silicon using a mixture of nitric acid and hydrofluoric acid in which less than 6 mols of hydrofluoric acid is used to etch one mol of silicon. The etching may be conducted at an elevated temperature, such as a temperature of at least 70 degrees Celsius.

公开(公告)号：US20150037923A1

公开(公告)日：2015-02-05

申请号：US14370321

申请日：2013-01-06

Applicant: 1366 TECHNOLOGIES, INC.

Inventor： Vladimir S. Tarasov ,  Ali Ersen ,  ERIC Stern ,  Jason M. Criscione ,  Emanuel M. Sachs

IPC: H01L31/0236 ,  H01L31/0248

CPC classification number: H01L31/02363 ,  H01L31/0248 ,  Y02E10/50

Abstract: Processes increase light absorption into silicon wafers by selectively changing the reflective properties of the bottom portions of light trapping cavity features. Modification of light trapping features includes: deepening the bottom portion, increasing the curvature of the bottom portion, and roughening the bottom portion, all accomplished through etching. Modification may also be by the selective addition of material at the bottom of cavity features. Different types of features in the same wafers may be treated differently. Some may receive a treatment that improves light trapping while another is deliberately excluded from such treatment. Some may be deepened, some roughened, some both. No alignment is needed to achieve this selectively. The masking step achieves self-alignment to previously created light trapping features due to softening and deformation in place.

Abstract translation: 通过选择性地改变光阱特征的底部的反射特性，工艺增加了对硅晶片的光吸收。 光捕获特征的改进包括：深化底部部分，增加底部部分的曲率，以及粗糙化底部部分，全部通过蚀刻来实现。 修改也可以通过在腔体特征的底部选择性地添加材料。 不同类型的相同晶片中的特征可以被不同地对待。 有些可能会接受改善光线捕获的治疗方法，而另一种方法被故意排除在这种治疗之外。 有些可能会加深，有些粗糙，有的两个。 不需要对准以选择性地实现。 掩蔽步骤由于在现场的软化和变形而实现了先前产生的光捕获特征的自对准。

公开(公告)号：US20120122266A1

公开(公告)日：2012-05-17

申请号：US13318971

申请日：2010-05-07

Applicant: Emanuel M. Sachs ,  Andrew M. Gabor

Inventor： Emanuel M. Sachs ,  Andrew M. Gabor

IPC: H01L31/18 ,  H01L21/302

CPC classification number: H01L31/022425 ,  H01L21/76802 ,  H01L31/02363 ,  H01L31/18 ,  Y02E10/50

Abstract: A porous lift off layer facilitates removal of films from surfaces, such as semiconductors. A film is applied over a patterned porous layer, the layer comprising openings typically larger than the film thickness. The porous material and the film are then removed from areas where film is not intended. The porous layer can be provided as a slurry, dried to open porosities, or fugitive particles within a field, which disassociate upon the application of heat or solvent. The film can be removed by etchant that enters through porosities where the film does not bridge the spaces between solid portions, so that the etchant attacks both film surfaces

Abstract translation: 多孔提升层有助于从诸如半导体的表面去除膜。 将膜施加在图案化的多孔层上，该层包括通常大于膜厚度的开口。 然后将多孔材料和膜从不需要膜的区域中取出。 多孔层可以作为浆料提供，干燥以打开孔隙，或场内的逸散颗粒，其在施加热或溶剂时解离。 可以通过蚀刻剂从薄膜不固定部分之间的空隙的孔隙中进入薄膜，从而使蚀刻剂侵袭两个薄膜表面

公开(公告)号：US20120067273A1

公开(公告)日：2012-03-22

申请号：US13299031

申请日：2011-11-17

Applicant: Emanuel M. Sachs ,  Richard L. Wallace ,  Eerik T. Hantsoo ,  Adam M. Lorenz ,  G. D. Stephen Hudelson ,  Ralf Jonczyk

Inventor： Emanuel M. Sachs ,  Richard L. Wallace ,  Eerik T. Hantsoo ,  Adam M. Lorenz ,  G. D. Stephen Hudelson ,  Ralf Jonczyk

IPC: C30B11/00 ,  C30B19/10

CPC classification number: B29C33/44 ,  C30B11/007 ,  C30B15/30 ,  C30B19/068 ,  C30B28/04 ,  C30B29/06

Abstract: A pressure differential is applied across a mold sheet and a semiconductor (e.g. silicon) wafer (e.g. for solar cell) is formed thereon. Relaxation of the pressure differential allows release of the wafer. The mold sheet may be cooler than the melt. Heat is extracted almost exclusively through the thickness of the forming wafer. The liquid and solid interface is substantially parallel to the mold sheet. The temperature of the solidifying body is substantially uniform across its width, resulting in low stresses and dislocation density and higher crystallographic quality. The mold sheet must allow flow of gas through it. The melt can be introduced to the sheet by: full area contact with the top of a melt; traversing a partial area contact of melt with the mold sheet, whether horizontal or vertical, or in between; and by dipping the mold into a melt. The grain size can be controlled by many means.

Abstract translation: 在模板上施加压差，在其上形成半导体（例如硅）晶片（例如，用于太阳能电池）。 压差的放松允许晶片的释放。 模具片可以比熔体更冷。 几乎完全通过成形晶片的厚度提取热量。 液体和固体界面基本上平行于模片。 凝固体的温度在其宽度上基本均匀，导致低应力和位错密度和更高的晶体学质量。 模板必须允许气体流过它。 可以通过以下方式将熔体引入片材：与熔体的顶部完全区域接触; 穿过熔体与模板的部分区域接触，无论是水平还是垂直的，或者在其间; 并将模具浸入熔体中。 可以通过许多方法控制晶粒尺寸。

公开(公告)号：US10549476B2

公开(公告)日：2020-02-04

申请号：US14345681

申请日：2012-09-22

Applicant: 1366 TECHNOLOGIES, INC.

Inventor： Emanuel M. Sachs ,  Peter E. Kane ,  Holly G. Gates ,  Damian W. Harris ,  Benjamin F. Polito ,  Hector A. Inirio

IPC: G03F7/00 ,  B29C59/02

Abstract: A workpiece is transported using a porous belt, which belt delivers a workpiece to a chuck, upon which the workpiece is held by vacuum. The belt can be porous PTFE. A flexible stamp is preheated, before it is applied to a workpiece, by drawing the stamp toward a heated plate, for instance by vacuum.

公开(公告)号：US10439095B2

公开(公告)日：2019-10-08

申请号：US15546030

申请日：2015-10-14

Applicant: 1366 TECHNOLOGIES INC.

Inventor： Ralf Jonczyk ,  Brian D. Kernan ,  G. D. Stephen Hudelson ,  Adam M. Lorenz ,  Emanuel M. Sachs

IPC: H01L21/00 ,  H01L31/18 ,  H01L31/0224 ,  H01L31/068 ,  H01L31/056 ,  H01L31/0216 ,  H01L31/0288 ,  C30B29/06 ,  C30B28/04 ,  C30B19/12 ,  C30B35/00 ,  C30B31/04 ,  C30B11/00 ,  C30B31/02

Abstract: A semiconductor wafer forms on a mold containing a dopant. The dopant dopes a melt region adjacent the mold. There, dopant concentration is higher than in the melt bulk. A wafer starts solidifying. Dopant diffuses poorly in solid semiconductor. After a wafer starts solidifying, dopant cannot enter the melt. Afterwards, the concentration of dopant in the melt adjacent the wafer surface is less than what was present where the wafer began to form. New wafer regions grow from a melt region whose dopant concentration lessens over time. This establishes a dopant gradient in the wafer, with higher concentration adjacent the mold. The gradient can be tailored. A gradient gives rise to a field that can function as a drift or back surface field. Solar collectors can have open grid conductors and better optical reflectors on the back surface, made possible by the intrinsic back surface field.

公开(公告)号：US20140113156A1

公开(公告)日：2014-04-24

申请号：US13990498

申请日：2011-12-01

Applicant: Ralf Jonczyk ,  Emanuel M. Sachs

Inventor： Ralf Jonczyk ,  Emanuel M. Sachs

IPC: H01L21/02

CPC classification number: H01L31/182 ,  C04B41/4539 ,  C04B41/5096 ,  C30B11/002 ,  C30B15/00 ,  C30B15/007 ,  C30B15/32 ,  C30B29/06 ,  H01L21/02002 ,  H01L21/02532 ,  H01L31/1804 ,  Y02E10/546 ,  Y02P70/521

Abstract: An interposer sheet can be used for making semiconductor bodies, such as of silicon, such as for solar cell use. It is free-standing, very thin, flexible, porous and able to withstand the chemical and thermal environment of molten semiconductor without degradation. It is typically of a ceramic material, such as silica, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, silicon carbonitride, silicon oxycarbonitride and others. It is provided between a forming surface of a mold sheet, and the molten material from which a semiconductor body will be formed. It may be secured to the forming surface or deposited upon the melt. The interposer sheet suppresses grain nucleation, and limits heat flow from the melt. It promotes separation of the semiconductor body from the forming surface. It can be fabricated before its use. Because free-standing and not adhered to the forming surface, problems of mismatch of CTE are minimized. The interposer sheet and semiconductor body are free to expand and contract relatively independently of the forming surface.

Abstract translation: 插入片可用于制造诸如硅的半导体本体，例如用于太阳能电池。 它是独立的，非常薄的，柔性的，多孔的并且能够耐受熔融半导体的化学和热环境而不降解。 它通常是陶瓷材料，例如二氧化硅，氮化硅，氮氧化硅，碳氧化硅，碳化硅，碳氮化硅，碳氮氧化硅等。 设置在模板的成形表面和将形成半导体本体的熔融材料之间。 它可以固定到成形表面或沉积在熔体上。 插入片抑制晶粒成核，并限制来自熔体的热流。 它促进半导体主体与成形表面的分离。 它可以在使用之前进行制造。 由于独立且不粘附到成型表面，CTE的失配问题被最小化。 插入片和半导体本体相对于成形表面相对自由地膨胀和收缩。

公开(公告)号：US08633052B2

公开(公告)日：2014-01-21

申请号：US12937810

申请日：2009-04-17

Applicant: Benjamin F. Polito ,  Holly G. Gates ,  Emanuel M. Sachs

Inventor： Benjamin F. Polito ,  Holly G. Gates ,  Emanuel M. Sachs

IPC: H01L21/00

CPC classification number: H01L31/182 ,  B29C43/021 ,  B29C43/222 ,  B29C59/02 ,  B29C2043/025 ,  B29C2043/3634 ,  B29C2043/3652 ,  B29C2043/465 ,  B29C2059/023 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L31/0236 ,  H01L31/02363 ,  Y02E10/50

Abstract: Patterned substrates for photovoltaic and other uses are made by pressing a flexible stamp upon a thin layer of resist material, which covers a substrate, such as a wafer. The resist changes phase or becomes flowable, flowing away from locations of impression, revealing the substrate, which is subjected to some shaping process, typically etching. Portions exposed by the stamp being are removed, and portions that protected by the resist, remain. A typical substrate is silicon, and a typical resist is a wax. Workpiece textures include extended grooves, discrete, spaced apart pits, and combinations and intermediates thereof. Platen or rotary patterning apparatus may be used. Rough and irregular workpiece substrates may be accommodated by extended stamp elements. Resist may be applied first to the workpiece, the stamp, or substantially simultaneously, in discrete locations, or over the entire surface of either. The resist dewets the substrate completely where desired.

Abstract translation: 用于光伏和其他用途的图案化基板是通过将柔性印模压在覆盖诸如晶片的基底的抗蚀剂材料薄层上而制成的。 抗蚀剂改变相位或变得可流动，从印模的位置流出，露出经受一些成形过程的基底，通常是蚀刻。 被邮票曝光的部分被去除，并且被抗蚀剂保护的部分保留。 典型的基底是硅，典型的抗蚀剂是蜡。 工件纹理包括延伸凹槽，离散的，间隔开的凹坑，以及它们的组合和中间体。 可以使用压板或旋转图案形成装置。 粗糙和不规则的工件衬底可以由延长的印模元件容纳。 抗蚀剂可以首先施加到工件，印模或基本上同时地在离散的位置，或者在两者的整个表面上。 抗蚀剂在需要时完全将基材脱模。

公开(公告)号：US20110146782A1

公开(公告)日：2011-06-23

申请号：US12937829

申请日：2009-04-17

Applicant: Andrew M. Gabor ,  Richard L. Wallace

Inventor： Andrew M. Gabor ,  Richard L. Wallace

IPC: H01L31/0224 ,  H01L31/18

CPC classification number: H01L31/1804 ,  H01L21/228 ,  H01L21/6715 ,  H01L31/022425 ,  H01L31/0288 ,  Y02E10/547 ,  Y02P70/521

Abstract: Methods exploiting a Self Aligned Cell (SAC) architecture for doping purposes, use the architecture to direct the deposition and application of either a dopant or a diffusion retarder. Doping is provided in regions that will become metallization for conducting fingers. Dopant may be treated directly into metallization grooves. Or, diffusion retarder may be provided in non-groove locations, and dopant may be provided over some or all of the entire wafer surface. Dopant and metal automatically go where desired, and in register with each other. The SAC architecture also includes concave surfaces for light absorbing regions of a cell, to reduce reflection of light energy, which regions may also be treated with dopant in the concavities, to result in semiconductor emitter lines. Alternatively, diffusion retarder may be treated into the concavities, leaving upper tips of ridges between the concavities exposed, thereby subject to deeper doping.

Abstract translation: 利用自对准单元（SAC）架构进行掺杂的方法，使用该架构来指导掺杂剂或扩散延迟器的沉积和应用。 在将成为导电手指的金属化的区域中提供掺杂。 掺杂剂可以直接处理成金属化槽。 或者，扩散延迟器可以设置在非凹槽位置，并且可以在整个晶片表面的一些或全部上提供掺杂剂。 掺杂剂和金属自动进入需要的地方，并相互注册。 SAC结构还包括用于单元的光吸收区域的凹面，以减少光能的反射，哪些区域也可以在凹部中用掺杂剂处理，以产生半导体发射线。 或者，扩散延迟器可以被处理成凹面，从而使暴露的凹部之间的脊的上部尖端留下更深的掺杂。

公开(公告)号：US10770613B2

公开(公告)日：2020-09-08

申请号：US16559971

申请日：2019-09-04

Applicant: 1366 TECHNOLOGIES INC.

Inventor： Ralf Jonczyk ,  Brian D. Kernan ,  G.D. Stephen Hudelson ,  Adam M. Lorenz ,  Emanuel M. Sachs

IPC: H01L31/06 ,  H01L31/00 ,  H01L31/062 ,  H01L31/113 ,  H01L31/18 ,  H01L31/0224 ,  C30B11/00 ,  C30B19/12 ,  C30B28/04 ,  C30B29/06 ,  C30B31/02 ,  C30B31/04 ,  C30B35/00 ,  H01L21/00 ,  H01L31/068 ,  H01L31/056 ,  H01L31/0216 ,  H01L31/0288

Abstract: A semiconductor wafer forms on a mold containing a dopant. The dopant dopes a melt region adjacent the mold. There, dopant concentration is higher than in the melt bulk. A wafer starts solidifying. Dopant diffuses poorly in solid semiconductor. After a wafer starts solidifying, dopant can not enter the melt. Afterwards, the concentration of dopant in the melt adjacent the wafer surface is less than what was present where the wafer began to form. New wafer regions grow from a melt region whose dopant concentration lessens over time. This establishes a dopant gradient in the wafer, with higher concentration adjacent the mold. The gradient can be tailored. A gradient gives rise to a field that can function as a drift or back surface field. Solar collectors can have open grid conductors and better optical reflectors on the back surface, made possible by the intrinsic back surface field.