公开(公告)号：US09362277B2

公开(公告)日：2016-06-07

申请号：US14175827

申请日：2014-02-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa Chi ,  Ajey Jacob ,  Abhijeet Paul

IPC: H01L21/8238 ,  H01L21/205 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/161 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.

Abstract translation: 公开了一种形成具有小占地面积的多值逻辑晶体管的方法和所得到的器件。 实施例包括在硅衬底上形成多个翅片，每个翅片用硬掩模覆盖; 用氧化物填充翅片和硬掩模之间的空间; 去除硬掩模并使每个翅片凹陷，在每个翅片上的氧化物中形成空腔; 在每个空腔中形成多个Si基层，其中Ge或C的百分比增加或掺杂剂浓度从底层到顶层的浓度降低; 执行CMP以平坦化到翅片的顶部; 将氧化物凹陷到具有等于每个Si基层的厚度的厚度的略微低于翅片顶部的深度; 以及在多个Si基层上形成高k栅极电介质和金属栅电极。

公开(公告)号：US09689084B2

公开(公告)日：2017-06-27

申请号：US14284932

申请日：2014-05-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Charles L. Arvin ,  Harry D. Cox ,  Eric D. Perfecto

IPC: C25D21/12 ,  C25D17/10

CPC classification number: C25D5/18 ,  C25D17/10 ,  C25D21/12

Abstract: Disclosed are electrodeposition systems and methods wherein at least three electrodes are placed in a container containing a plating solution. The electrodes are connected to a polarity-switching unit and include a first electrode, a second electrode and a third electrode. The polarity-switching unit establishes a constant polarity state between the first and second electrodes in the solution during an active plating mode, wherein the first electrode has a negative polarity and the second electrode has a positive polarity, thereby allowing a plated layer to form on a workpiece at the first electrode. The polarity-switching unit further establishes an oscillating polarity state between the second and third electrodes during a non-plating mode (i.e., when the first electrode is removed from the plating solution), wherein the second electrode and the third electrode have opposite polarities that switch at regular, relatively fast, intervals, thereby limiting degradation of the second electrode and/or the plating solution.

公开(公告)号：US09316916B2

公开(公告)日：2016-04-19

申请号：US12419403

申请日：2009-04-07

Applicant: Kuang-Jung Chen ,  Wu-Song Huang ,  Wai-kin Li

Inventor： Kuang-Jung Chen ,  Wu-Song Huang ,  Wai-kin Li

IPC: G03F7/207 ,  G03F7/40 ,  G03F7/00 ,  G03F7/20 ,  G03F7/38

CPC classification number: G03F7/40 ,  G03F7/0035 ,  G03F7/2024 ,  G03F7/203 ,  G03F7/2041 ,  G03F7/38

Abstract: A method to mitigate resist pattern critical dimension (CD) variation in a double-exposure process generally includes forming a photoresist layer over a substrate; exposing the photoresist layer to a first radiation; developing the photoresist layer to form a first pattern in the photoresist layer; forming a topcoat layer over the photoresist layer; exposing the topcoat layer and the photoresist layer to a second radiation; removing the topcoat layer; and developing the photoresist layer to form a second pattern in the photoresist layer.

Abstract translation: 减轻双曝光工艺中抗蚀剂图案临界尺寸（CD）变化的方法通常包括在衬底上形成光致抗蚀剂层; 将光致抗蚀剂层暴露于第一辐射; 显影光致抗蚀剂层以在光致抗蚀剂层中形成第一图案; 在光致抗蚀剂层上形成顶涂层; 将顶涂层和光致抗蚀剂层暴露于第二辐射; 去除顶涂层; 并且在光致抗蚀剂层中显影光致抗蚀剂层以形成第二图案。

公开(公告)号：US20140042502A1

公开(公告)日：2014-02-13

申请号：US13957587

申请日：2013-08-02

Applicant: Globalfoundries Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

Abstract: One illustrative method disclosed herein includes removing a portion of a sacrificial sidewall spacer to thereby expose at least a portion of the sidewalls of a sacrificial gate electrode and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode. In this example, the method also includes forming a sacrificial gap fill material above the liner layer, exposing and removing the sacrificial gate electrode to thereby define a gate cavity that is laterally defined by the liner layer, forming a replacement gate structure, removing the sacrificial gap fill material and forming a low-k sidewall spacer adjacent the liner layer. A device is also disclosed that includes a gate cap layer, a layer of silicon nitride or silicon oxynitride positioned on each of two upstanding portions of a gate insulation layer and a low-k sidewall spacer positioned on the layer of silicon nitride or silicon oxynitride.

Abstract translation: 本文公开的一种说明性方法包括去除牺牲侧壁间隔物的一部分，从而暴露牺牲栅电极的侧壁的至少一部分，并在牺牲栅电极的暴露的侧壁上形成衬垫层。 在该示例中，该方法还包括在衬垫层之上形成牺牲间隙填充材料，暴露和去除牺牲栅极电极，从而限定由衬里层横向限定的栅极腔，形成替代栅极结构，去除牺牲层 间隙填充材料并形成邻近衬层的低k侧壁间隔物。 还公开了一种器件，其包括栅极覆盖层，位于栅极绝缘层的两个直立部分中的每一个上的氮化硅或氮氧化硅层，以及位于氮化硅或氮氧化硅层上的低k侧壁间隔物。