公开(公告)号：US11631767B2

公开(公告)日：2023-04-18

申请号：US17470104

申请日：2021-09-09

申请人： Semiconductor Manufacturing International (Beijing) Corporation ,  Semiconductor Manufacturing International (Shanghai) Corporation

发明人： Fei Zhou

IPC分类号： H01L21/8234 ,  H01L29/78 ,  H01L21/308 ,  H01L29/66

摘要： A semiconductor structure and a method for forming a semiconductor structure are disclosed. One form a semiconductor structure includes: a substrate, comprising a first region used to form a well region and a second region used to form a drift region, wherein the first region is adjacent to the second region; and a fin, protruding out of the substrate, wherein the fins comprise first fins located at a junction of the first region and the second region and second fins located on the second region, and a quantity of the second fins is greater than a quantity of the first fins.

公开(公告)号：US11631743B2

公开(公告)日：2023-04-18

申请号：US17223238

申请日：2021-04-06

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Abraham Yoo ,  Jisong Jin

IPC分类号： H01L29/417 ,  H01L23/535 ,  H01L29/78 ,  H01L21/768 ,  H01L29/66 ,  H01L29/40 ,  H01L23/522

摘要： A semiconductor structure and a forming method of a semiconductor structure are provided. One form of the forming method includes: providing a base, where a discrete gate structure is formed on the base, a spacer is formed on a side wall of the gate structure, and a source/drain doped layer is formed in the base on two sides of the gate structure, and a bottom dielectric layer covering the source/drain doped layer is formed on the two sides of the gate structure; forming a bottom source/drain plug running through the bottom dielectric layer above the source/drain doped layer, a source/drain cap layer located on a top surface of the bottom source/drain plug, a gate cap layer located on a top surface of the gate structure, and an etching barrier layer located between the gate cap layer and the source/drain cap layer and covering a top surface of the spacer; forming a top dielectric layer covering the gate cap layer, the source/drain cap layer, and the etching barrier layer on the bottom dielectric layer; forming a top source/drain plug that runs through the source/drain cap layer and the top dielectric layer and that is in contact with the bottom source/drain plug; and forming a gate plug that runs through the gate cap layer and the top dielectric layer and that is in contact with the gate structure. Embodiments of the present disclosure help improve the performance of the semiconductor structure.

公开(公告)号：US11626289B2

公开(公告)日：2023-04-11

申请号：US16932102

申请日：2020-07-17

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Xi Lin ,  Sheng Wang

IPC分类号： H01L21/311 ,  H01L21/768

摘要： A method for forming a semiconductor structure includes providing a substrate, forming a stop layer over a surface of the substrate, forming a dielectric layer over a surface of the stop layer, forming a first opening in the dielectric layer and exposing a portion of the stop layer, modifying the portion of the stop layer exposed at a bottom of the first opening to form a modification layer, and removing the modification layer to form a second opening from the first opening.

公开(公告)号：US20230100058A1

公开(公告)日：2023-03-30

申请号：US17955955

申请日：2022-09-29

申请人： Semiconductor Manufacturing International (Beijing) Corporation ,  Semiconductor Manufacturing International (Shanghai) Corporation

发明人： Hailong YU ,  Bo SU ,  Hansu OH

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L21/02 ,  H01L21/311 ,  H01L21/285

摘要： Semiconductor structure and forming method thereof are provided. The forming method includes: providing a substrate; forming a plurality of initial composite layers on a portion of the substrate; forming a plurality of source and drain layers on surfaces of the plurality of channel layers exposed by a first opening and grooves by using a selective epitaxial growth process, the plurality of source and drain layers being parallel to a first direction and distributed along a second direction, the second direction being parallel to a normal direction of the substrate, and gaps being between adjacent source and drain layers; forming contact layers on surfaces of the plurality of source and drain layers and in the gaps; and forming a conductive structure on a surface of a contact layer on a source and drain layer of the plurality of source and drain layers.

公开(公告)号：US11587848B2

公开(公告)日：2023-02-21

申请号：US17037051

申请日：2020-09-29

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Yi Lu ,  Xiaohui Zhuang ,  Yihui Lin ,  Liang Wang ,  Le Li ,  Kaige Gao ,  Wenjie Zhu ,  Jialin Zhao

IPC分类号： H01L23/48 ,  H01L21/48 ,  H01L21/768 ,  H01L23/522

摘要： Semiconductor structure and its fabrication method are provided. The method includes providing a substrate, where the substrate includes a first region having a first metal structure and a second region having a second metal structure; forming a device layer on each of top surfaces of the substrate, the first metal structure and the second metal structure; forming a first through hole in the device layer at the first region, where the first through hole exposes at least a portion of surfaces of the first metal structure, and forming a second through hole in the device layer at the second region, where the second through hole passes through the first device and exposes at least a portion of surfaces of the second metal structure; and using a selective metal growth process, forming a first plug in the first through hole and forming a second plug in the second through hole.

公开(公告)号：US11587836B2

公开(公告)日：2023-02-21

申请号：US17022364

申请日：2020-09-16

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Song Bai ,  Qi Liang Ma ,  Tao Song ,  Xuan Li

IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/308 ,  H01L29/78

摘要： A semiconductor structure and its fabrication method are provided in the present disclosure. The method includes providing a layer to-be-etched, including first regions and second regions. The method further includes forming a plurality of discrete first sacrificial layers on the layer to-be-etched, where a plurality of openings is between the plurality of first sacrificial layers and includes first openings on the first regions. The method further includes forming initial sidewall spacer structures on sidewalls of the plurality of first sacrificial layers, where the initial sidewall spacer structures include first sidewall spacers, and the first sidewall spacers fill the first openings. The method further includes, using the first sidewall spacers as an alignment mark, forming a first mask layer on the layer to-be-etched and the initial sidewall spacer structures, where the first mask layer exposes a portion of the layer to-be-etched and a portion of the initial sidewall spacer structures.

公开(公告)号：US11569131B2

公开(公告)日：2023-01-31

申请号：US16857447

申请日：2020-04-24

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Fei Zhou

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66

摘要： A semiconductor device and its fabrication method are provided in the present disclosure. The method includes providing a substrate; forming a plurality of fins spaced apart on the substrate; forming a dummy gate structure across the plurality of fins and on the substrate; forming a first sidewall spacer on a sidewall of the dummy gate structure; forming an interlayer dielectric layer on the substrate and the fins, and on a portion of a sidewall of the first sidewall spacer, where a top of the interlayer dielectric layer is lower than a top of the first sidewall spacer; and forming a second sidewall spacer on the interlayer dielectric layer and on a sidewall of the first sidewall spacer.

公开(公告)号：US11538685B2

公开(公告)日：2022-12-27

申请号：US16929809

申请日：2020-07-15

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Xiamei Tang ,  Wei Shi ,  Tao Dou ,  Bo Su ,  Youcun Hu

IPC分类号： H01L21/033

摘要： A method of forming a semiconductor structure includes providing a to-be-etched layer, forming a core layer over the to-be-etched layer, the core layer including a first trench extending along a first direction, forming a sidewall spacer layer on a top surface of the core layer and on sidewalls and a bottom surface of the first trench, forming a block cut structure in the first trench after forming the sidewall spacer layer, and after forming the block cut structure, etching back the sidewall spacer layer until exposing the top surface of the core layer, thereby leaving a sidewall spacer on the sidewalls of the first trench. The block cut structure extends through the first trench along a second direction. The second direction and the first direction are different. The block cut structure includes a first block-cut layer and a second block-cut layer.

公开(公告)号：US11532632B2

公开(公告)日：2022-12-20

申请号：US17162176

申请日：2021-01-29

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Yong Li

IPC分类号： H01L27/11 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/423

摘要： A semiconductor device includes a base substrate including an NMOS region and a PMOS region. The PMOS region includes a first P-type region and a second P-type region. The semiconductor device also includes an interlayer dielectric layer, a gate structure formed through the interlayer dielectric layer and including an N-type region gate structure formed in the NMOS region, a first gate structure formed in the first P-type region and connected to the N-type region gate structure, and a second gate structure formed in the second P-type region and connected to the first gate structure. The direction from the N-type region gate structure to the second gate structure is an extending direction of the N-type region opening, and along a direction perpendicular to the extending direction of the N-type region opening, the width of the first gate structure is larger than the width of the second gate structure.

公开(公告)号：US20220365275A1

公开(公告)日：2022-11-17

申请号：US17742974

申请日：2022-05-12

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Xiaojun CHEN ,  Honglin ZENG ,  Xia FENG ,  Dongsheng ZHANG ,  Xiage YIN ,  Jiaheng WU

IPC分类号： G02B6/12 ,  G02B6/124 ,  G02B6/13

摘要： A method of forming a semiconductor structure includes: providing an initial substrate having a first region and a second region; forming a first substrate on the initial substrate; forming a first insulating layer on the first substrate; forming a second substrate on the first insulating layer; removing the second substrate in the second region to form a second insulating layer on the first insulating layer in the second region; and forming a plurality of passive devices on the second insulating layer in the second region and forming a plurality of active devices on the second substrate in the first region.