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公开(公告)号:US12083705B2
公开(公告)日:2024-09-10
申请号:US17414680
申请日:2019-12-12
申请人: SILTRONIC AG
发明人: Axel Beyer , Stefan Welsch
CPC分类号: B28D5/0064 , B24B27/0633 , B28D5/0082 , B28D5/045 , H01L21/67092 , H01L21/67253 , B23D59/00 , B28D5/00 , B28D5/0058 , B28D5/007 , B28D5/04 , B28D7/00 , H01L21/0201
摘要: Semiconductor wafers are produced from a workpiece by means of a wire saw, by feeding the workpiece through an arrangement of wires tensioned between wire guide rollers and divided into wire groups, the wires moving in a running direction producing kerfs as wires engage the workpiece. For each of the wire groups, a placement error of the kerfs of the wire groups determined, and for each of the wire groups compensating movements of the wires of the wire group are induced as a function of the placement error, in a direction perpendicular to the running direction of the wires during feeding of the workpiece through the arrangement of wires, by activating at least one drive element.
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公开(公告)号:US20240234125A9
公开(公告)日:2024-07-11
申请号:US18546434
申请日:2022-02-04
申请人: SILTRONIC AG
发明人: Georg Pietsch , Joachim Junge
CPC分类号: H01L21/02019 , B24B7/228 , B24D7/06 , B28D5/045 , B28D7/02
摘要: A method produces wafers from a cylindrical ingot of semiconductor material having an axis and an indexing notch in an outer surface of the cylindrical ingot and parallel to the axis. The method includes, in the order specified: (a) simultaneous removal of a multiplicity of sliced wafers from the cylindrical ingot by multi-wire slicing in the presence of a cutting agent; (b) etching of the sliced wafers with an alkaline etchant in an etching bath at a temperature of 20° C. to 50° C. and for a residence time, such that the material removed from each of the sliced wafers is less than 5/1000 of an initial wafer thickness; and (c) grinding of the etched wafers by simultaneous double-disk grinding using an annular abrasive covering.
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公开(公告)号:US20240186168A1
公开(公告)日:2024-06-06
申请号:US18554226
申请日:2022-03-31
申请人: SILTRONIC AG
发明人: Thomas Stettner
CPC分类号: H01L21/68 , H01L21/02381 , H01L21/0262
摘要: A process produces semiconductor wafers with epitaxial layer deposited from a gas phase in a deposition chamber. The process includes placing a substrate wafer on a susceptor with circular perimeter by a robot that moves the substrate wafer into a placement position and places it on the susceptor with a corrective precept causing a center of the substrate wafer not to lie above a center of the susceptor; and depositing the epitaxial layer on the substrate wafer. A first number of substrate wafers having a specific resistance which falls within a first range are moved into the placement position with a first corrective precept, and a second number of substrate wafers having a specific resistance which falls within a second range are moved by the robot with a second corrective precept, differs from the first corrective precept.
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公开(公告)号:US20240105523A1
公开(公告)日:2024-03-28
申请号:US18264252
申请日:2022-02-04
申请人: SILTRONIC AG
IPC分类号: H01L21/66
CPC分类号: H01L22/12 , H01L21/324
摘要: A method tests the stress robustness of a semiconductor substrate. The method includes: forming a nitride layer on a surface of the semiconductor substrate, the nitride layer being directly deposited on the surface of the semiconductor substrate or on a native oxide layer that is interposed on the surface; cooling the semiconductor substrate and the nitride layer; patterning the nitride layer into a patterned nitride by photolithography including a step of reactive ion etching with ions produced from a gas, which includes hydrogen or a hydrogen compound or both; processing the patterned nitride and the semiconductor substrate at a temperature of not less than 800° C. and not more than 1300° C. in a nitrogen atmosphere to induce the formation of dislocations at an interface between the patterned nitride and the semiconductor substrate; and evaluating at least one property that is related to the formed dislocations.
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5.
公开(公告)号:US20230286067A1
公开(公告)日:2023-09-14
申请号:US18008185
申请日:2021-05-20
申请人: Siltronic AG
发明人: Peter Wiesner , Wolfgang Gmach , Robert Kreuzeder
CPC分类号: B23D61/185 , B23D59/04 , B28D5/0064 , B28D5/045
摘要: A method cuts slices from workpieces using a wire saw having a wire array, which is tensioned in a plane between two wire guide rollers supported between fixed and floating bearings and having a chamber and a shell. The workpiece is fed through the wire array along a feed direction perpendicular to a workpiece axis, while simultaneously changing the shells' lengths by adjusting a temperature of the chambers with a first cooling fluid in accordance with a first correction profile specifying a change in the shells' lengths based on the depth of cut. The floating bearings are simultaneously axially moved by adjusting a temperature of the fixed bearings with a second cooling fluid in accordance with a second correction profile, which specifies a travel of the floating bearings based on the depth of cut. The first correction profile and the second correction profile are opposed to a shape deviation.
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公开(公告)号:US11598020B2
公开(公告)日:2023-03-07
申请号:US17279623
申请日:2019-09-27
申请人: Siltronic AG
发明人: Alexander Molchanov
摘要: An apparatus pulls a single crystal of semiconductor material by the Czochralski (CZ) method from a melt. The apparatus includes: a crucible that accommodates the melt; a resistance heater around the crucible; a camera system for observing a phase boundary between the melt and a growing single crystal, the camera system having an optical axis; a heat shield in frustoconical form with a narrowing diameter in a region at its lower end and arranged above the crucible and surrounding the growing single crystal; and an annular element, which is configured to capture particles, that projects inward from an inner side face of the heat shield and has an arrestor edge directed upward at an inner end of the annular element. The optical axis of the camera system runs between the arrestor edge and the growing single crystal. The annular element is releasably connected to the heat shield.
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公开(公告)号:US11538683B2
公开(公告)日:2022-12-27
申请号:US16765479
申请日:2018-11-28
申请人: Siltronic AG
发明人: Joerg Haberecht , Rene Stein , Stephan Heinrich
IPC分类号: H01L21/02 , H01L21/205 , H01L21/67
摘要: A method deposits an epitaxial layer on a front side of a semiconductor wafer having monocrystalline material. The method includes: providing the semiconductor wafer; arranging the semiconductor wafer on a susceptor; heating the semiconductor wafer to a deposition temperature using thermal radiation directed to the front side and to the rear side of the semiconductor wafer; conducting a deposition gas over the front side of the semiconductor wafer; and selectively reducing an intensity of a portion of the thermal radiation that is directed to the rear side of the semiconductor wafer, as a result of which first partial regions at an edge of the semiconductor wafer, in the first partial regions a growth rate of the epitaxial layer is greater than in adjacent second partial regions given uniform temperature of the semiconductor wafer owing to an orientation of the monocrystalline material, are heated more weakly.
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公开(公告)号:US20220349086A1
公开(公告)日:2022-11-03
申请号:US17762101
申请日:2020-09-15
申请人: Siltronic AG
发明人: Rolf Schmid , Helmut Bergmann , Werner Joedecke
摘要: An apparatus is configured to pull a single crystal of semiconductor material from a melt contained in a crucible. The apparatus includes: a rotatable pulling shaft; a rotatable crucible shaft; a double worm gear between a drive and the pulling shaft; and a further double worm gear between a further drive and the crucible shaft.
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公开(公告)号:US20220267926A1
公开(公告)日:2022-08-25
申请号:US17614214
申请日:2020-04-29
申请人: SILTRONIC AG
IPC分类号: C30B25/12 , H01L23/544 , H01L21/02 , H01L21/687 , C30B25/10 , C23C16/458 , C23C16/46
摘要: Variations in wafer thickness due to non-uniform CVD depositions at angular positions corresponding to crystallographic orientation of the wafer are reduced by providing a ring below the susceptor having inward projections at azimuthal positions which reduce radiant heat impinging upon the wafer at positions of increased deposition.
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公开(公告)号:US11161217B2
公开(公告)日:2021-11-02
申请号:US16340223
申请日:2017-10-27
申请人: SILTRONIC AG
发明人: Vladimir Dutschke
IPC分类号: B24B37/04 , H01L21/306
摘要: Semiconductor wafers are polished on both sides between polishing pads of a Shore A hardness of at least 80 and a compressibility of less than 3%, attached to upper and lower polishing plates, the polishing pads attached to the upper and lower polishing plates by bonding the polishing pads to the plates, and positioning an intermediate pad having a compressibility of at least 3% between the two bonded polishing pads as an intermediate layer and then pressing together the two polishing pads with the intermediate pad situated therebetween for a period of time.
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