公开(公告)号：US08775719B2

公开(公告)日：2014-07-08

申请号：US12807996

申请日：2010-09-17

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

IPC分类号： G06F12/00

CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1075 ,  G11C2216/22

摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A parallel interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the parallel interface at the rising edge and the falling edge of the synchronizing clock. The parallel interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.

摘要翻译： 非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。 并行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。 数据在同步时钟的上升沿和下降沿在并行接口上传输。 并行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由 地址代码 读取一个非易失性存储器阵列可能会中断读取另一个。 一次读取操作具有两个子地址，一个命令之前传送一个。

公开(公告)号：US20110072200A1

公开(公告)日：2011-03-24

申请号：US12807996

申请日：2010-09-17

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

IPC分类号： G06F12/02 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1075 ,  G11C2216/22

摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A parallel interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the parallel interface at the rising edge and the falling edge of the synchronizing clock. The parallel interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.

摘要翻译： 非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。 并行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。 数据在同步时钟的上升沿和下降沿在并行接口上传输。 并行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由 地址代码 读取一个非易失性存储器阵列可能会中断读取另一个。 一次读取操作具有两个子地址，一个命令之前传送一个。

公开(公告)号：US07372736B2

公开(公告)日：2008-05-13

申请号：US11391662

申请日：2006-03-28

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

IPC分类号： G11C16/04 ,  H01L29/76 ,  H01L23/544

CPC分类号： H01L27/11521 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14 ,  H01L27/115 ,  H01L27/11524

摘要： A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.

摘要翻译： 非易失性存储器阵列具有单个晶体管闪存单元和可集成在同一衬底上的两个晶体管EEPROM存储单元。 非易失性存储单元具有低耦合系数的浮动栅极，以允许更小的存储单元。 浮置栅极放置在隧道绝缘层之上，浮动栅极与源极区域和漏极区域的边缘对准，并且具有由源极漏极的边缘的宽度限定的宽度。 浮动栅极和控制栅极具有小于50％的相对小的耦合比，以允许非易失性存储单元的缩放。 非易失性存储单元用通道热电子编程进行编程，并以相对高的电压用Fowler Nordheim隧道擦除。

公开(公告)号：US07120064B2

公开(公告)日：2006-10-10

申请号：US11036961

申请日：2005-01-14

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

IPC分类号： G11C16/04

CPC分类号： H01L27/115 ,  G11C11/005 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

公开(公告)号：US07102929B2

公开(公告)日：2006-09-05

申请号：US11036835

申请日：2005-01-14

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma ,  Koucheng Wu

IPC分类号： G11C16/04

CPC分类号： H01L27/115 ,  G11C11/005 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

摘要翻译： 公开了一种新颖的基于FLASH的EEPROM单元，解码器和布局方案，以消除单元阵列中的面积消耗的划分三阱，并允许字节擦除和字节程序用于高P / E周期。 此外，用于EEPROM部件的处理兼容FLASH单元可以与FLASH和ROM部件集成，从而实现了优异的组合，单片，非易失性存储器。 与所有以前的技术不同，ROM，EEPROM和FLASH本发明的新颖的组合非易失性存储器或任何两个的组合由一个统一的，完全兼容的，高度可扩展的BN +单元和统一过程组成。 此外，其单元操作方案在P / E操作期间具有零阵列开销和零扰动。 该新颖的组合非易失性存储器旨在满足那些需要灵活的写入大小（以字节，页面和块为单位）以低成本的市场的需求。

公开(公告)号：US07064978B2

公开(公告)日：2006-06-20

申请号：US10351180

申请日：2003-01-24

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

IPC分类号： G11C16/04 ,  H01L29/76 ,  H01L23/544

CPC分类号： H01L27/11521 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14 ,  H01L27/115 ,  H01L27/11524

摘要： A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.

摘要翻译： 非易失性存储器阵列具有单个晶体管闪存单元和可集成在同一衬底上的两个晶体管EEPROM存储单元。 非易失性存储单元具有低耦合系数的浮动栅极，以允许更小的存储单元。 浮置栅极放置在隧道绝缘层之上，浮动栅极与源极区域和漏极区域的边缘对准，并且具有由源极漏极的边缘的宽度限定的宽度。 浮动栅极和控制栅极具有小于50％的相对小的耦合比，以允许非易失性存储单元的缩放。 非易失性存储单元用通道热电子编程进行编程，并以相对高的电压用Fowler Nordheim隧道擦除。

公开(公告)号：US6009022A

公开(公告)日：1999-12-28

申请号：US189109

申请日：1998-11-09

申请人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu

发明人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu

IPC分类号： G11C5/14 ,  G11C7/12 ,  G11C8/08 ,  G11C16/30 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C16/30 ,  G11C5/147 ,  G11C8/08

摘要： An on-chip system receives raw positive and negative voltages from voltage pumps and provides CMOS-compatible bandgap-type positive and negative reference voltages from which regulated positive and negative Vpp and Vpn voltages are generated. A bitline (BL) regulator and a sourceline (SL) regulator receive Vpp and generate a plurality of BL voltages and SL voltages, and use feedback to compare potential at selected BL nodes and SL nodes to a reference potential using a multi-stage differential input differential output comparator. Reference voltages used to create BL and SL potentials may be varied automatically as a function of addressed cell locations to compensate for ohmic losses associated with different cell array positions. The system includes positive and negative wordline (WL) regulators that each use feedback from selected WL nodes. The system further includes a WL detector and magnitude detector for Vdd and Vpp, and can accommodate multiple level memory (MLC) cells by slewing reference voltages used to output regulated voltages. The system preferably is fabricated on the same IC chip as the address logic and memory array using the regulated potentials.

摘要翻译： 片上系统从电压泵接收原始的正负电压，并提供CMOS兼容的带隙型正和负参考电压，从而产生调节的正负Vpp和Vpn电压。 位线（BL）调节器和源极（SL）调节器接收Vpp并产生多个BL电压和SL电压，并且使用反馈来使用多级差分输入将所选BL节点和SL节点处的电位与参考电位进行比较 差分输出比较器。 用于产生BL和SL电位的参考电压可以根据寻址的单元位置自动变化，以补偿与不同单元阵列位置相关联的欧姆损耗。 该系统包括正和负字母（WL）调节器，每个调节器使用来自所选WL节点的反馈。 该系统还包括用于Vdd和Vpp的WL检测器和幅度检测器，并且可以通过用于输出调节电压的回转参考电压来适应多电平存储器（MLC）单元。 该系统优选地在与使用调节电位的地址逻辑和存储器阵列相同的IC芯片上制造。

公开(公告)号：US5835420A

公开(公告)日：1998-11-10

申请号：US884251

申请日：1997-06-27

申请人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu

发明人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu

IPC分类号： G11C5/14 ,  G11C7/12 ,  G11C8/08 ,  G11C16/30 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C16/30 ,  G11C5/147 ,  G11C8/08

摘要： An on-chip system receives raw positive and negative voltages from voltage pumps and provides CMOS-compatible bandgap-type positive and negative reference voltages from at least one of which regulated positive and negative Vpp and Vpn voltages are generated. A bitline (BL) regulator and a sourceline (SL) regulator receive Vpp and generate a plurality of BL voltages and SL voltages, and use feedback to compare potential at selected BL nodes and SL nodes to a reference potential using a multi-stage differential input differential output comparator. Reference voltages used to create BL and SL potentials may be varied automatically as a function of addressed cell locations to compensate for ohmic losses associated with different cell array positions. The system includes positive and negative wordline (WL) regulators that each use feedback from selected WL nodes. The system further includes a WL detector and magnitude detector for Vdd and Vpp, and can accommodate multiple level memory (MLC) cells by slewing reference voltages used to output regulated voltages. The system preferably is fabricated on the same IC chip as the address logic and memory array using the regulated potentials.

摘要翻译： 片上系统从电压泵接收原始的正负电压，并提供CMOS兼容的带隙型正和负参考电压，从而产生调节的正负Vpp和Vpn电压中的至少一个。 位线（BL）调节器和源极（SL）调节器接收Vpp并产生多个BL电压和SL电压，并且使用反馈来使用多级差分输入将所选BL节点和SL节点处的电位与参考电位进行比较 差分输出比较器。 用于产生BL和SL电位的参考电压可以根据寻址的单元位置自动变化，以补偿与不同单元阵列位置相关联的欧姆损耗。 该系统包括正和负字母（WL）调节器，每个调节器使用来自所选WL节点的反馈。 该系统还包括用于Vdd和Vpp的WL检测器和幅度检测器，并且可以通过用于输出调节电压的回转参考电压来适应多电平存储器（MLC）单元。 该系统优选地在与使用调节电位的地址逻辑和存储器阵列相同的IC芯片上制造。

公开(公告)号：US5682350A

公开(公告)日：1997-10-28

申请号：US726670

申请日：1996-10-07

申请人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu

发明人： Peter W. Lee ,  Hsing-Ya Tsao ,  Fu-Chang Hsu

IPC分类号： G11C8/08 ,  G11C8/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/34 ,  H01L27/115 ,  G11C16/00

CPC分类号： G11C16/3409 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0416 ,  G11C16/0491 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/34 ,  G11C16/3404 ,  G11C16/3413 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3431 ,  G11C8/08 ,  G11C8/10 ,  H01L27/115 ,  G11C16/24 ,  G11C2211/5642 ,  G11C2211/5644 ,  G11C2216/20 ,  G11C7/1006 ,  G11C7/18 ,  G11C8/00 ,  G11C8/14

摘要： A flash memory includes a bank of flash transistors forming a plurality of rows and a plurality of columns, each flash transistor having a gate, drain and source, where the gates of flash transistors in each row are coupled to common wordlines, the drains of flash transistors in each column are coupled to common metal 1 lines divided into even metal 1 lines and odd metal 1 lines and the sources of the flash transistors are coupled to a common sourceline. A set of first selection transistors are coupled between even metal 1 lines and metal 2 lines having a pitch twice that of said metal 1 lines and controlled by a first select signal to selectively couple the even metal 1 lines to the metal 2 lines. A set of second selection transistors are coupled between odd metal 1 lines and the metal 2 lines and controlled by a second select signal to selectively couple the odd metal 1 lines to the metal 2 lines. In one embodiment, the set of first selection transistors and the set of second selection transistors are large in comparison to the flash transistors. Advantages of the invention include improved selection of memory cells, higher memory cell density and lower resistance in the memory cell selection circuitry.

摘要翻译： 闪速存储器包括形成多行和多列的闪存晶体管组，每个闪存晶体管具有栅极，漏极和源极，其中每行中的闪存晶体管的栅极耦合到公共字线，闪存的漏极 每列中的晶体管耦合到分为偶数金属1线和奇数金属1线的公共金属1线，并且闪存晶体管的源耦合到公共源极线。 一组第一选择晶体管耦合在偶数金属1线和金属2线之间，金属2线具有两倍于所述金属1线的间距，并由第一选择信号控制，以选择性地将偶数金属1线耦合到金属2线。 一组第二选择晶体管耦合在奇数金属1线和金属2线之间，并由第二选择信号控制，以将奇数金属1线选择性地耦合到金属2线。 在一个实施例中，与闪存晶体管相比，该组第一选择晶体管和该组第二选择晶体管较大。 本发明的优点包括存储器单元的改进选择，更高的存储单元密度和较低的存储单元选择电路中的电阻。

公开(公告)号：US08996785B2

公开(公告)日：2015-03-31

申请号：US12807997

申请日：2010-09-17

申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

IPC分类号： G06F12/00 ,  G11C16/32 ,  G11C16/04

CPC分类号： G11C16/32 ,  G11C16/0408

摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the serial interface at the rising edge and the falling edge of the synchronizing clock. The serial interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.

摘要翻译： 非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。 串行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。 数据在同步时钟的上升沿和下降沿在串行接口上​​传输。 串行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由 地址代码 读取一个非易失性存储器阵列可能会中断读取另一个。 一次读取操作具有两个子地址，一个命令之前传送一个。