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公开(公告)号：US20240014260A1
公开(公告)日：2024-01-11
申请号：US18332837
申请日：2023-06-12
发明人： Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Chih-Chang Cheng , Ruey-Hsin Liu
IPC分类号： H01L29/06 , H01L29/40 , H01L29/861 , H01L27/08 , H01L23/535 , H01L29/36 , H01L29/66
CPC分类号： H01L29/0646 , H01L29/404 , H01L29/8611 , H01L29/0623 , H01L29/063 , H01L28/20 , H01L27/0802 , H01L23/535 , H01L29/36 , H01L29/405 , H01L29/66136 , H01L29/7835
摘要： High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a substrate, a first doped region disposed in the substrate and doped with a first doping polarity, and a second doped region disposed in the substrate and horizontally outside the first doped region. The second doped region is doped with a second doping polarity opposite to the first doping polarity. The semiconductor device further includes a third doped region disposed completely within the first doped region. The third doped region is doped with the second doping polarity. The semiconductor device further includes a first isolation structure disposed over the first doped region and spaced apart from the second doped region and the third doped region, a second isolation structure disposed over the first doped region and the third doped region, and a resistor disposed over the first isolation structure.
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公开(公告)号：US20220352325A1
公开(公告)日：2022-11-03
申请号：US17867012
申请日：2022-07-18
发明人： Yao-Chung Chang , Chun Lin Tsai , Ru-Yi Su , Wei Wang , Wei-Chen Yang
IPC分类号： H01L29/417 , H01L29/66
摘要： Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.
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公开(公告)号：US20210399087A1
公开(公告)日：2021-12-23
申请号：US17462403
申请日：2021-08-31
发明人： Karthick Murukesan , Wen-Chih Chiang , Chun Lin Tsai , Ker-Hsiao Huo , Kuo-Ming Wu , Po-Chih Chen , Ru-Yi Su , Shiuan-Jeng Lin , Yi-Min Chen , Hung-Chou Lin , Yi-Cheng Chiu
IPC分类号： H01L29/06 , H01L29/66 , H01L29/78 , H01L21/8234 , H01L29/10 , H03K19/0185 , H01L27/088
摘要： Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.
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公开(公告)号：US10411681B2
公开(公告)日：2019-09-10
申请号：US15863229
申请日：2018-01-05
发明人： Man-Ho Kwan , Fu-Wei Yao , Ru-Yi Su , King-Yuen Wong
IPC分类号： H03K5/08 , H01L27/088 , H01L29/778
摘要： A device includes a first transistor having a first source terminal, a first drain terminal, and a first gate terminal; and a second transistor having a second source terminal, a second drain terminal, and a second gate terminal. The second source terminal is coupled to the first gate terminal and the first source terminal is coupled to the second gate terminal. The first transistor has a first threshold voltage, and the second transistor has a second threshold voltage different from the first threshold voltage.
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公开(公告)号：US10319644B2
公开(公告)日：2019-06-11
申请号：US15460894
申请日：2017-03-16
发明人： Man-Ho Kwan , Fu-Wei Yao , Ru-Yi Su , Chun Lin Tsai , Alexander Kalnitsky
IPC分类号： H01L21/8252 , H01L21/02 , H01L21/265 , H01L21/761 , H01L21/768 , H01L21/8258 , H01L27/06 , H01L29/06 , H01L29/16 , H01L29/205 , H01L23/535 , H01L29/778 , H01L29/78 , H01L29/866 , H01L29/20
摘要： In some embodiments, a semiconductor structure includes a first device and a second device. The first device has a first surface. The first device includes a first active region defined by a first material system. The second device has a second surface. The second surface is coplanar with the first surface. The second device includes a second active region defined by a second material system. The second material system is different from the first material system.
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公开(公告)号：US20160308036A1
公开(公告)日：2016-10-20
申请号：US15191745
申请日：2016-06-24
发明人： Ker-Hsiao Huo , Fu-Chih Yang , Jen-Hao Yeh , Chun Lin Tsai , Chih-Chang Cheng , Ru-Yi Su
IPC分类号： H01L29/739 , H01L29/08 , H01L29/06 , H01L29/66 , H01L29/78 , H01L21/265 , H01L21/762 , H01L29/10 , H01L29/49
CPC分类号： H01L29/7394 , H01L21/26533 , H01L21/76243 , H01L21/76283 , H01L29/063 , H01L29/0649 , H01L29/0653 , H01L29/0865 , H01L29/0882 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/42368 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/66325 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7824 , H01L2924/0002 , H01L2924/00
摘要： A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), and more particularly an insulated gate bipolar junction transistor (IGBT), is disclosed. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.
摘要翻译： 公开了一种高压金属氧化物半导体横向扩散器件（HV LDMOS），特别是绝缘栅双极结型晶体管（IGBT）。 该器件包括半导体衬底，形成在衬底上的栅极结构，在栅极结构的任一侧上的衬底中形成的源极和漏极，在衬底中形成的第一掺杂阱和形成在第一衬底中的第二掺杂阱 好。 栅极，源极，第二掺杂阱，第一阱的一部分和漏极结构的一部分被硅衬底中的深沟槽隔离特征和注入的氧层包围。
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公开(公告)号：US20160056303A1
公开(公告)日：2016-02-25
申请号：US14932465
申请日：2015-11-04
发明人： Jen-Hao Yeh , Chih-Chang Cheng , Ru-Yi Su , Ker-Hsiao Huo , Po-Chih Chen , Fu-Chih Yang , Chun Lin Tsai
IPC分类号： H01L29/808 , H01L29/06
CPC分类号： H01L29/808 , H01L27/088 , H01L27/098 , H01L29/063 , H01L29/0692 , H01L29/404 , H01L29/66901
摘要： A device includes a p-well region, and a first High-Voltage N-type Well (HVNW) region and a second HVNW region contacting opposite edges of the p-well region. A P-type Buried Layer (PBL) has opposite edges in contact with the first HVNW region and the second HVNW region. An n-type buried well region is underlying the PBL. The p-well region and the n-type buried well region are in contact with a top surface and a bottom surface, respectively, of the PBL. The device further includes a n-well region in a top portion of the p-well region, an n-type source region in the n-well region, a gate stack overlapping a portion of the p-well region and a portion of the second HVNW region, and a channel region under the gate stack. The channel region interconnects the n-well region and the second HVNW region.
摘要翻译： 一种器件包括p阱区和接触p阱区的相对边缘的第一高电压N型阱（HVNW）区域和第二HVNW区域。 P型掩埋层（PBL）具有与第一HVNW区域和第二HVNW区域接触的相对边缘。 一个n型掩埋井区是PBL的底层。 p阱区域和n型掩埋阱区域分别与PBL的顶表面和底表面接触。 该器件还包括在p阱区的顶部中的n阱区，n阱区中的n型源极区，与p阱区的一部分重叠的栅极堆叠 第二HVNW区域和栅极堆叠下的沟道区域。 沟道区域互连n阱区域和第二HVNW区域。
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8.发明授权公开(公告)号：US09214547B2
公开(公告)日：2015-12-15
申请号：US14051655
申请日：2013-10-11
发明人： Ker Hsiao Huo , Chih-Chang Cheng , Ru-Yi Su , Jen-Hao Yeh , Fu-Chih Yang , Chun Lin Tsai
IPC分类号： H01L29/66 , H01L29/78 , H01L21/265 , H01L21/762 , H01L29/423 , H01L29/06 , H01L29/10
CPC分类号： H01L29/7394 , H01L21/26533 , H01L21/76243 , H01L21/76283 , H01L29/063 , H01L29/0649 , H01L29/0653 , H01L29/0865 , H01L29/0882 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/42368 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/66325 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7824 , H01L2924/0002 , H01L2924/00
摘要： A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.
摘要翻译： 在本公开中提供了高电压金属氧化物半导体横向扩散器件（HV LDMOS），特别是绝缘栅双极结型晶体管（IGBT）及其制造方法。 该器件包括半导体衬底，形成在衬底上的栅极结构，在栅极结构的任一侧上的衬底中形成的源极和漏极，在衬底中形成的第一掺杂阱和形成在第一衬底中的第二掺杂阱 好。 栅极，源极，第二掺杂阱，第一阱的一部分和漏极结构的一部分被硅衬底中的深沟槽隔离特征和注入的氧层包围。
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公开(公告)号：US20140235028A1
公开(公告)日：2014-08-21
申请号：US14179623
申请日：2014-02-13
发明人： Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Chih-Chang Cheng , Ruey-Hsin Liu
CPC分类号： H01L29/0649 , H01L21/26513 , H01L21/74 , H01L21/761 , H01L21/76202 , H01L23/528 , H01L27/0676 , H01L27/0802 , H01L28/20 , H01L29/0692 , H01L29/456 , H01L29/6609 , H01L29/8605 , H01L29/868
摘要： Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.
摘要翻译： 提供一种高压半导体器件，其包括形成在衬底中的PIN二极管结构。 PIN二极管包括位于第一掺杂阱和第二掺杂阱之间的本征区。 第一和第二掺杂阱具有与内部区域相反的掺杂极性和更大的掺杂浓度水平。 半导体器件包括形成在第一掺杂阱的一部分上的绝缘结构。 半导体器件包括形成在绝缘结构上的细长电阻器件。 电阻器件分别设置在电阻器件的相对端处的第一和第二部分。 半导体器件包括形成在电阻器件上的互连结构。 互连结构包括：电耦合到第一掺杂阱的第一接触和电耦合到位于第一和第二部分之间的电阻器的第三部分的第二接触。
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公开(公告)号：US11908905B2
公开(公告)日：2024-02-20
申请号：US17867012
申请日：2022-07-18
发明人： Yao-Chung Chang , Chun Lin Tsai , Ru-Yi Su , Wei Wang , Wei-Chen Yang
IPC分类号： H01L29/417 , H01L29/66 , H01L29/20 , H01L29/205 , H01L29/778 , H01L29/868
CPC分类号： H01L29/417 , H01L29/41741 , H01L29/6609 , H01L29/2003 , H01L29/205 , H01L29/7788 , H01L29/868
摘要： Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.
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