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1.发明授权Systems and methods for measuring inductor current in a switching DC-to-DC converter 有权用于测量开关DC-DC转换器中的电感电流的系统和方法公开(公告)号：US09461537B1
公开(公告)日：2016-10-04
申请号：US14252244
申请日：2014-04-14
申请人： Cirrus Logic, Inc.
发明人： Xin Zhao , Ku He , John L. Melanson , Xiaofan Fei
CPC分类号： H02M3/04 , G01R19/0084 , G01R19/0092 , G01R31/40 , H02M3/156 , H02M2001/0009
摘要： A switch control circuit may be utilized for a sequence of switching events: a first event to activate a first switch and deactivate a second switch, wherein a current of an inductor coupled to the first switch and the second switch increases during the first event and has a positive value at an end of the first event; a second event to deactivate the first switch and activate the second switch, wherein the current of an inductor coupled to the first switch and the second switch decreases during the second event; and an impedance event during one of the first event and the second event such that during one of the first event and the second event, the impedance event causes an impedance of the one of the first switch and the second switch to decrease.
摘要翻译： 开关控制电路可以用于一系列切换事件：第一事件以激活第一开关并去激活第二开关，其中耦合到第一开关和第二开关的电感器的电流在第一事件期间增加并具有 在第一个事件结束时的正值; 第二事件，用于停用第一开关并激活第二开关，其中耦合到第一开关和第二开关的电感器的电流在第二事件期间减小; 以及在第一事件和第二事件之一期间的阻抗事件，使得在第一事件和第二事件之一期间，阻抗事件引起第一开关和第二开关中的一个的阻抗减小。
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公开(公告)号：US20160072465A1
公开(公告)日：2016-03-10
申请号：US14481201
申请日：2014-09-09
申请人： Cirrus Logic, Inc.
发明人： Tejasvi Das , Xin Zhao , Ted Burk , Ku He , John L. Melanson , Xiaofan Fei
CPC分类号： H03G3/20 , H03G3/001 , H03G3/002 , H03G3/3005 , H03G3/3089
摘要： A signal path may operate in one of a plurality of gain modes such that for each gain mode, the product of a digital gain and an analog signal gain of the signal path associated with the particular gain mode are approximately equal to a fixed path gain. During each of one or more calibration phases, a calibration system may measure analog signals at a plurality of nodes of the first path portion, calculate an actual analog gain associated with the gain mode based on the analog signals measured at the plurality of nodes, calculate an error between the fixed path gain and a mathematical product of the actual analog gain associated with the gain mode and the digital gain associated with the gain mode, and modify at least one of the digital gain and the analog gain associated with the gain mode in conformity with the error.
摘要翻译： 信号路径可以以多种增益模式之一操作，使得对于每个增益模式，与特定增益模式相关联的信号路径的数字增益和模拟信号增益的乘积近似等于固定路径增益。 在一个或多个校准阶段的每一个期间，校准系统可以测量第一路径部分的多个节点处的模拟信号，基于在多个节点处测量的模拟信号来计算与增益模式相关联的实际模拟增益，计算 固定路径增益与与增益模式相关联的实际模拟增益与与增益模式相关联的数字增益的数学乘积之间的误差，并且修改与增益模式相关联的数字增益和模拟增益中的至少一个 符合错误。
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公开(公告)号：US09214948B2
公开(公告)日：2015-12-15
申请号：US14255912
申请日：2014-04-17
申请人： Cirrus Logic, Inc.
发明人： Ku He , Xin Zhao , Xiaofan Fei
CPC分类号： H03M1/002 , H03M1/0809 , H03M1/181 , H03M1/36
摘要： A comparator tracking scheme for an analog-to-digital converter (ADC) may implement a dynamic window size by varying, over time, a number of comparators powered up to convert an analog input signal to a digital output signal. A comparator-tracking scheme may be implemented, for example, in a controller coupled to a plurality of comparators in an ADC. For example, the controller may determine a window size for the ADC and determine a window position for the ADC. The controller may then activate comparators of the ADC within a window centered at the window position and having a width of the window size. The controller may determine a window size by analyzing an output of a filter. When the filter output indicates a rapidly changing analog input signal, the controller may dynamically increase a window size of the ADC, which may increase a number of comparators powered on.
摘要翻译： 用于模数转换器（ADC）的比较器跟踪方案可以通过随时间变化多个比较器供电以将模拟输入信号转换为数字输出信号来实现动态窗口尺寸。 比较器跟踪方案可以例如在耦合到ADC中的多个比较器的控制器中实现。 例如，控制器可以确定ADC的窗口大小并确定ADC的窗口位置。 然后，控制器可以在以窗口位置为中心并且具有窗口大小的宽度的窗口内激活ADC的比较器。 控制器可以通过分析滤波器的输出来确定窗口大小。 当滤波器输出指示快速变化的模拟输入信号时，控制器可以动态增加ADC的窗口大小，这可能会增加多个比较器上电。
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公开(公告)号：US20150295584A1
公开(公告)日：2015-10-15
申请号：US14680830
申请日：2015-04-07
申请人： Cirrus Logic, Inc.
发明人： Tejasvi Das , John L. Melanson , John C. Tucker , Xiaofan Fei
CPC分类号： H03M1/002 , H03M1/0845 , H03M1/66 , H03M1/662 , H03M1/68 , H03M1/70 , H03M1/785 , H03M3/32 , H03M3/392 , H03M3/414 , H03M3/416 , H03M3/50
摘要： In accordance with embodiments of the present disclosure, a processing system may include a plurality of processing paths including a first processing path and a second processing path, a digital-to-analog stage output, and a controller. The first processing path may include a first digital-to-analog converter for converting the digital input signal into a first intermediate analog signal, the first digital-to-analog converter configured to operate in a high-power state and a low-power state. The second processing path may include a second digital-to-analog converter for converting a digital input signal into a second intermediate analog signal. The digital-to-analog stage output may be configured to generate an analog signal comprising a sum of the first intermediate analog signal and the second intermediate analog signal. The controller may be configured to operate the first digital-to-analog converter in the lower-power state when a magnitude of the digital input signal is below a threshold magnitude.
摘要翻译： 根据本公开的实施例，处理系统可以包括多个处理路径，包括第一处理路径和第二处理路径，数模转换阶段输出和控制器。 第一处理路径可以包括用于将数字输入信号转换成第一中间模拟信号的第一数模转换器，第一数模转换器被配置为在大功率状态和低功率状态 。 第二处理路径可以包括用于将数字输入信号转换成第二中间模拟信号的第二数模转换器。 数模转换级输出可以被配置为产生包括第一中间模拟信号和第二中间模拟信号之和的模拟信号。 控制器可以被配置为当数字输入信号的幅度低于阈值幅度时，在较低功率状态下操作第一数模转换器。
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公开(公告)号：US09680488B2
公开(公告)日：2017-06-13
申请号：US15050857
申请日：2016-02-23
申请人： Cirrus Logic, Inc.
发明人： Tejasvi Das , John L. Melanson , John C. Tucker , Xiaofan Fei
CPC分类号： H03M1/002 , H03M1/0845 , H03M1/66 , H03M1/662 , H03M1/68 , H03M1/70 , H03M1/785 , H03M3/32 , H03M3/392 , H03M3/414 , H03M3/416 , H03M3/50
摘要： In accordance with embodiments of the present disclosure, a processing system may include a plurality of processing paths including a first processing path and a second processing path, a digital-to-analog stage output, and a controller. The first processing path may include a first digital-to-analog converter for converting the digital input signal into a first intermediate analog signal, the first digital-to-analog converter configured to operate in a high-power state and a low-power state. The second processing path may include a second digital-to-analog converter for converting a digital input signal into a second intermediate analog signal. The digital-to-analog stage output may be configured to generate an analog signal comprising a sum of the first intermediate analog signal and the second intermediate analog signal. The controller may be configured to operate the first digital-to-analog converter in the lower-power state when a magnitude of the digital input signal is below a threshold magnitude.
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公开(公告)号：US09306588B2
公开(公告)日：2016-04-05
申请号：US14680830
申请日：2015-04-07
申请人： Cirrus Logic, Inc.
发明人： Tejasvi Das , John L. Melanson , John C. Tucker , Xiaofan Fei
CPC分类号： H03M1/002 , H03M1/0845 , H03M1/66 , H03M1/662 , H03M1/68 , H03M1/70 , H03M1/785 , H03M3/32 , H03M3/392 , H03M3/414 , H03M3/416 , H03M3/50
摘要： In accordance with embodiments of the present disclosure, a processing system may include a plurality of processing paths including a first processing path and a second processing path, a digital-to-analog stage output, and a controller. The first processing path may include a first digital-to-analog converter for converting the digital input signal into a first intermediate analog signal, the first digital-to-analog converter configured to operate in a high-power state and a low-power state. The second processing path may include a second digital-to-analog converter for converting a digital input signal into a second intermediate analog signal. The digital-to-analog stage output may be configured to generate an analog signal comprising a sum of the first intermediate analog signal and the second intermediate analog signal. The controller may be configured to operate the first digital-to-analog converter in the lower-power state when a magnitude of the digital input signal is below a threshold magnitude.
摘要翻译： 根据本公开的实施例，处理系统可以包括多个处理路径，包括第一处理路径和第二处理路径，数模转换阶段输出和控制器。 第一处理路径可以包括用于将数字输入信号转换成第一中间模拟信号的第一数模转换器，第一数模转换器被配置为在大功率状态和低功率状态 。 第二处理路径可以包括用于将数字输入信号转换成第二中间模拟信号的第二数模转换器。 数模转换级输出可以被配置为产生包括第一中间模拟信号和第二中间模拟信号之和的模拟信号。 控制器可以被配置为当数字输入信号的幅度低于阈值大小时，在较低功率状态下操作第一数模转换器。
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公开(公告)号：US09853539B1
公开(公告)日：2017-12-26
申请号：US14243261
申请日：2014-04-02
申请人： Cirrus Logic, Inc.
发明人： Xin Zhao , Ku He , Xiaofan Fei
CPC分类号： H02M3/04 , H02M3/156 , H02M2001/0009
摘要： A switch control circuit may be utilized for a sequence of switching events occurring in an order of a first event, a second event, a third event, and a fourth event: the first event to activate the first switch and deactivate the second switch wherein an inductor current increases during the first event and has a positive value at an end of the first event, the second event to deactivate the first switch and activate the second switch wherein the switch control circuit maintains the current above zero during the second event, the third event to activate the first switch and deactivate the second switch, and the fourth event to deactivate the first switch and activate the second switch wherein the current decreases to a value below zero at an end of the fourth event and when the current reaches zero, a zero crossing time point is defined.
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公开(公告)号：US09831843B1
公开(公告)日：2017-11-28
申请号：US14204793
申请日：2014-03-11
申请人： Cirrus Logic, Inc.
发明人： Tejasvi Das , Bharath Kumar Thandri , Anand Ilango , Aniruddha Satoskar , Daniel John Allen , Xiaofan Fei
CPC分类号： H03G3/20 , H03G3/001 , H03G3/002 , H03G3/02 , H03G3/3005 , H03G3/3026 , H03M1/66 , H03M1/70
摘要： An audio playback path of an audio apparatus includes a digital modulator, a digital-to-analog converter (DAC), and a power amplifier. The digital modulator receives a playback signal corresponding to playback audio content and generates a digital input signal in accordance with the playback signal. The DAC receives the audio input signal and generates an analog preamplifier signal. The power amplifier generates an audio output signal in accordance with the preamplifier signal and an analog attenuation determined by the analog attenuation signal. The apparatus may include a volume control input to receive a volume control signal and a playback controller configured to perform operations including generating an analog attenuation signal in accordance with the volume control signal, monitoring a playback state indicated by the playback parameters, and responsive to detecting the playback state satisfying the playback criterion, modifying a selected playback parameter to improve a performance parameter of the playback path.
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公开(公告)号：US09337795B2
公开(公告)日：2016-05-10
申请号：US14481201
申请日：2014-09-09
申请人： Cirrus Logic, Inc.
发明人： Tejasvi Das , Xin Zhao , Ted Burk , Ku He , John L. Melanson , Xiaofan Fei
CPC分类号： H03G3/20 , H03G3/001 , H03G3/002 , H03G3/3005 , H03G3/3089
摘要： A signal path may operate in one of a plurality of gain modes such that for each gain mode, the product of a digital gain and an analog signal gain of the signal path associated with the particular gain mode are approximately equal to a fixed path gain. During each of one or more calibration phases, a calibration system may measure analog signals at a plurality of nodes of the first path portion, calculate an actual analog gain associated with the gain mode based on the analog signals measured at the plurality of nodes, calculate an error between the fixed path gain and a mathematical product of the actual analog gain associated with the gain mode and the digital gain associated with the gain mode, and modify at least one of the digital gain and the analog gain associated with the gain mode in conformity with the error.
摘要翻译： 信号路径可以以多种增益模式之一操作，使得对于每个增益模式，与特定增益模式相关联的信号路径的数字增益和模拟信号增益的乘积近似等于固定路径增益。 在一个或多个校准阶段的每一个期间，校准系统可以测量第一路径部分的多个节点处的模拟信号，基于在多个节点处测量的模拟信号来计算与增益模式相关联的实际模拟增益，计算 固定路径增益与与增益模式相关联的实际模拟增益与与增益模式相关联的数字增益的数学乘积之间的误差，并且修改与增益模式相关联的数字增益和模拟增益中的至少一个 符合错误。
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10.发明授权公开(公告)号：US09301046B1
公开(公告)日：2016-03-29
申请号：US14039662
申请日：2013-09-27
申请人： Cirrus Logic, Inc.
发明人： Tejasvi Das , Xiaofan Fei , Miao Song
IPC分类号： H04R3/00
CPC分类号： H04R3/04 , H04R1/1041
摘要： A control circuit coupled to a differential audio output stage may, responsive to a transition in a power supply voltage generated by a power supply, modify at least one of: (i) a first bandwidth associated with the power supply; (ii) a second bandwidth associated with a common-mode voltage generator for generating a desired output common-mode voltage based on the power supply voltage; and (iii) a third bandwidth associated with a common-mode feedback loop of the audio-output stage for setting an actual common-mode voltage at each of the pair of differential output terminals based on the desired output common-mode voltage; such that the second bandwidth is greater than or substantially equal to the first bandwidth during the transition and the third bandwidth is greater than or substantially equal to the second bandwidth during the transition.
摘要翻译： 耦合到差分音频输出级的控制电路可以响应于由电源产生的电源电压的转变来修改以下至少一个：（i）与电源相关联的第一带宽; （ii）与共模电压发生器相关联的第二带宽，用于基于所述电源电压产生期望的输出共模电压; 以及（iii）与所述音频输出级的共模反馈回路相关联的第三带宽，用于基于所述期望的输出共模电压来设置所述一对差分输出端中的每一对的实际共模电压; 使得第二带宽大于或基本上等于转换期间的第一带宽，并且第三带宽在转换期间大于或基本等于第二带宽。
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