公开(公告)号：US5792708A

公开(公告)日：1998-08-11

申请号：US611585

申请日：1996-03-06

申请人： Mei Sheng Zhou ,  Lap Chan ,  Young-Tong Tsai

发明人： Mei Sheng Zhou ,  Lap Chan ,  Young-Tong Tsai

IPC分类号： H01L21/3213 ,  H01L21/08

CPC分类号： H01L21/32137

摘要： A method for forming a residue free patterned polysilicon layer upon a high step height patterned substrate layer. First, there is provided a semiconductor substrate having formed thereon a high step height patterned substrate layer. Formed upon the high step height patterned substrate layer is a polysilicon layer, and formed upon the polysilicon layer is a patterned photoresist layer. The patterned photoresist layer exposes portions of the polysilicon layer at a lower step level of the high step height patterned substrate layer. The polysilicon layer is then patterned through the patterned photoresist layer as an etch mask employing an anisotropic first etch process to yield a patterned polysilicon layer upon the surface of the high step height patterned substrate layer and polysilicon residues at the lower step level of the high step height patterned substrate layer. The anisotropic first etch process is a Reactive Ion Etch (RIE) anisotropic first etch process which simultaneously passivates the exposed sidewall edges of the patterned polysilicon layer. Finally, the polysilicon residues formed at the lower step level of the high step height patterned substrate layer are removed through an isotropic second etch process. The isotropic second etch process is a Reactive Ion Etch (RIE) isotropic second etch process which employs hydrogen bromide (HBr) and sulfur hexafluoride (SF6) as the reactant gases.

摘要翻译： 一种用于在高台阶高度图案化衬底层上形成无残留图案化多晶硅层的方法。 首先，提供在其上形成有高台阶高度图案化基板层的半导体基板。 形成在高台阶高度图案化衬底层上的是多晶硅层，并且在多晶硅层上形成图案化的光致抗蚀剂层。 图案化的光致抗蚀剂层在高阶高度图案化衬底层的较低台阶处暴露多晶硅层的部分。 然后通过图案化的光致抗蚀剂层将多晶硅层图案化为使用各向异性第一蚀刻工艺的蚀刻掩模，以在高阶高度图案化衬底层的表面上产生图案化多晶硅层，并在高级步骤的较低级别处产生多晶硅残余物 高度图案化衬底层。 各向异性第一蚀刻工艺是反应离子蚀刻（RIE）各向异性第一蚀刻工艺，其同时钝化图案化多晶硅层的暴露的侧壁边缘。 最后，通过各向同性的第二蚀刻工艺去除在高阶高度图案化衬底层的较低台阶处形成的多晶硅残余物。 各向同性第二蚀刻工艺是使用溴化氢（HBr）和六氟化硫（SF6）作为反应气体的反应离子蚀刻（RIE）各向同性第二蚀刻工艺。

公开(公告)号：US06251781B1

公开(公告)日：2001-06-26

申请号：US09374312

申请日：1999-08-16

申请人： Mei Sheng Zhou ,  Guo-Qin Xu ,  Lap Chan

发明人： Mei Sheng Zhou ,  Guo-Qin Xu ,  Lap Chan

IPC分类号： H01L2144

CPC分类号： H01L21/76874 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating single and dual damascene copper interconnects is achieved. A semiconductor substrate layer is provided. Conductive traces are provided in an isolating dielectric layer. An intermetal dielectric layer is deposited overlying the conductive traces and the isolating dielectric layer. The intermetal dielectric layer is patterned to form trenches to expose the top surfaces of the underlying conductive traces. A barrier layer is deposited overlying the intermetal dielectric layer, the exposed conductive traces, and within the trenches. A platinum ionic seed solution is coated inside the trenches and overlying the barrier layer. A platinum seed layer is deposited from the ionic seed solution by exposing the platinum ionic seed solution to ultraviolet light. A copper layer is deposited by electroless plating to form copper interconnects, where the copper layer is only deposited overlying the platinum seed layer in the trenches, and where the deposition stops before the copper layer fills the trenches. The exposed barrier layer is polished down to the top surface of the intermetal dielectric layer. An encapsulation layer is deposited overlying the copper interconnects and the intermetal dielectric layer to complete the fabrication of the integrated circuit device.

摘要翻译： 实现了制造单和双镶嵌铜互连的方法。 提供半导体衬底层。 导电迹线设置在隔离电介质层中。 沉积覆盖导电迹线和隔离电介质层的金属间电介质层。 图案化金属间电介质层以形成沟槽以暴露下面的导电迹线的顶表面。 覆盖在金属间电介质层，暴露的导电迹线和沟槽内的阻挡层被沉积。 将铂离子种子溶液涂覆在沟槽内并覆盖阻挡层。 通过将铂离子种子溶液暴露于紫外光，从离子种子溶液沉积铂种子层。 通过无电镀沉积铜层以形成铜互连，其中铜层仅沉积在沟槽中的铂种子层上方，并且在铜层填充沟槽之前沉积停止。 暴露的阻挡层被抛光到金属间电介质层的顶表面。 沉积覆盖在铜互连和金属间电介质层上的封装层，以完成集成电路器件的制造。

公开(公告)号：US6121130A

公开(公告)日：2000-09-19

申请号：US192338

申请日：1998-11-16

申请人： Chee Tee Chua ,  Yuan-Ping Lee ,  Mei Sheng Zhou ,  Lap Chan

发明人： Chee Tee Chua ,  Yuan-Ping Lee ,  Mei Sheng Zhou ,  Lap Chan

IPC分类号： H01L21/268 ,  H01L21/3105 ,  H01L21/312 ,  H01L21/314 ,  H01L21/768 ,  H01L21/469

CPC分类号： H01L21/76825 ,  H01L21/02137 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/268 ,  H01L21/31058 ,  H01L21/3122 ,  H01L21/76801 ,  H01L21/76834

摘要： A process for curing low-k spin-on dielectric layers based on alkyl silsesquioxane polymers by laser scanning is described wherein curing is achieved by both photothermal and photochemical mechanisms. The layers are deposited by spin deposition, dried and cured by raster scanning with a pulsed laser at energies between 0.1 and 1 Joules/cm.sup.2. Because the laser causes heating of the layer, a nitrogen jet is applied in the wake of the scanning laser beam to rapidly cool the layer and to inhibit oxidation and moisture absorption. The laser induced heating also assists in the discharge of moisture and by-products of the polymerization process. The laser operates at wavelengths between 200 and 400 nm. Insulative layers such as silicon oxide are sufficiently transparent at these so that oxide segments overlying the polymer layer do not inhibit the curing process. Implementation of the laser scanning feature is readily incorporated into an existing spin-on deposition and curing tool.

摘要翻译： 描述了通过激光扫描固化基于烷基倍半硅氧烷聚合物的低k自旋电介质层的方法，其中通过光热和光化学机理实现固化。 通过旋转沉积沉积这些层，通过用0.1至1焦耳/ cm2的能量的脉冲激光进行光栅扫描来干燥和固化。 因为激光引起层的加热，所以在扫描激光束之后施加氮气喷射以快速冷却层并抑制氧化和吸湿。 激光诱导加热还有助于排出水分和聚合过程的副产物。 激光器工作在200和400 nm之间的波长。 绝缘层例如氧化硅在这些处是足够透明的，使得覆盖聚合物层的氧化物段不会阻碍固化过程。 激光扫描特征的实现容易地并入现有的旋涂沉积和固化工具中。

公开(公告)号：US09262732B2

公开(公告)日：2016-02-16

申请号：US13166501

申请日：2011-06-22

申请人： Bin Duan ,  Lap Chan

发明人： Bin Duan ,  Lap Chan

IPC分类号： G06Q10/06 ,  H04W64/00

CPC分类号： G06Q10/0631 ,  H04W64/006

摘要： A system and method of tracking action items in an enterprise data processing environment. The method includes receiving, by a client from a server, an action item that includes a location. The method further includes performing a check-in, by the client, at the location related to the action item. The method further includes performing a check-out, by the client, related to the action item. The method further includes changing, by the client, the status of the action item. In this manner, a database of action items and statuses may be developed for more effective business collaboration and business management.

摘要翻译： 跟踪企业数据处理环境中的动作项目的系统和方法。 该方法包括由客户端从服务器接收包括位置的动作项目。 该方法还包括由客户端在与该动作项目相关的位置处执行登记。 该方法还包括由客户端执行与该动作项目相关的退房。 该方法还包括由客户端改变动作项目的状态。 以这种方式，可以开发一个行动项目和状态的数据库，用于更有效的业务协作和业务管理。

公开(公告)号：US20140123068A1

公开(公告)日：2014-05-01

申请号：US13661687

申请日：2012-10-26

申请人： Lap Chan

发明人： Lap Chan

IPC分类号： G06F3/048

CPC分类号： G06F3/04817 ,  G06F3/0482 ,  G06F3/0486 ,  G06F3/04886 ,  H04M1/72519

摘要： Example systems and methods of managing content are described. In one implementation, a method accesses a first set of data, if second set of data, and menu data. The menu data is associated with multiple menu actions relevant to the first set of data and the second set of data. The method generates display data that allows a display device to present the first set of data, the second set of data, and the menu to a user such that the menu is positioned between the first set of data and the second set of data. The method receives a user selection of a menu action and, based on the user selection, generates a graphical object that allows the user to indicate whether to apply the selected menu action to the first set of data or the second set of data.

摘要翻译： 描述了管理内容的示例系统和方法。 在一个实现中，一种方法访问第一组数据，如果是第二组数据，则菜单数据。 菜单数据与与第一组数据和第二组数据相关的多个菜单操作相关联。 该方法产生允许显示设备向用户呈现第一组数据，第二组数据和菜单的显示数据，使得菜单位于第一组数据和第二组数据之间。 该方法接收菜单动作的用户选择，并且基于用户选择，生成允许用户指示是否将所选择的菜单动作应用于第一组数据或第二组数据的图形对象。

公开(公告)号：US07932152B2

公开(公告)日：2011-04-26

申请号：US12025789

申请日：2008-02-05

申请人： Will Wong ,  Lap Chan ,  Alan Lek

发明人： Will Wong ,  Lap Chan ,  Alan Lek

IPC分类号： H01L21/8234

CPC分类号： H01L21/28202 ,  H01L21/28035 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method of forming an integrated circuit structure on a substrate, the substrate includes a primary region and a secondary region. A first layer of a first material of a first thickness is formed over the substrate. A portion of the first layer is removed over the primary region to expose the substrate. The structure is exposed to an oxidizing medium. This forms a second layer, for example, of an oxide material primary region of the substrate. The second layer has a second thickness. Additionally, at least a portion of said first layer is converted to a third layer, for example, of an oxynitride material. The third layer has a third thickness.

摘要翻译： 一种在基板上形成集成电路结构的方法，所述基板包括主区域和次区域。 在衬底上形成第一厚度的第一材料的第一层。 第一层的一部分在主区域上被去除以暴露衬底。 该结构暴露于氧化介质。 这形成例如基板的氧化物材料主区域的第二层。 第二层具有第二厚度。 另外，所述第一层的至少一部分被转换成例如氮氧化物材料的第三层。 第三层具有第三厚度。

公开(公告)号：US20050196931A1

公开(公告)日：2005-09-08

申请号：US11123748

申请日：2005-05-04

申请人： Jian Li ,  Lap Chan ,  Purakh Verma ,  Jia Zheng ,  Shao-fu Chu

发明人： Jian Li ,  Lap Chan ,  Purakh Verma ,  Jia Zheng ,  Shao-fu Chu

IPC分类号： H01L21/331 ,  H01L29/737

CPC分类号： H01L29/66242 ,  H01L29/737

摘要： A lateral heterojunction bipolar transistor (HBT), comprising a semiconductor substrate having having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.

摘要翻译： 一种横向异质结双极晶体管（HBT），包括在半导体衬底上具有第一绝缘层的半导体衬底。 基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。 半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。 基底结构形成在基底沟槽中。 通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。 基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

公开(公告)号：US20050156269A1

公开(公告)日：2005-07-21

申请号：US11081908

申请日：2005-03-15

申请人： Pooi Lee ,  Kin Pey ,  Alex See ,  Lap Chan

发明人： Pooi Lee ,  Kin Pey ,  Alex See ,  Lap Chan

IPC分类号： H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L29/49 ,  H01L27/095

CPC分类号： H01L29/665 ,  H01L21/26506 ,  H01L21/28518 ,  H01L29/4933

摘要： A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature. It also reduces nickel enhanced poly-silicon grain growth to prevent layer inversion. Some embodiments of this nickel salicide process may be used in an otherwise standard salicide process, to form integrated circuit devices with low resistivity transistor gate electrodes and source/drain contacts.

公开(公告)号：US20050145953A1

公开(公告)日：2005-07-07

申请号：US10752454

申请日：2004-01-05

申请人： Lap Chan ,  Jia Zheng ,  Purakh Verma ,  Jian Li ,  Shao-fu Chu

发明人： Lap Chan ,  Jia Zheng ,  Purakh Verma ,  Jian Li ,  Shao-fu Chu

IPC分类号： H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L31/113

CPC分类号： H01L29/66242 ,  H01L21/8249 ,  H01L27/0623

摘要： A method of manufacturing a BiCMOS integrated circuit including a CMOS transistor having a gate structure, and a heterojunction bipolar transistor having an extrinsic base structure. A substrate is provided, and a polysilicon layer is formed over the substrate. The gate structure and the extrinsic base structure are formed in the polysilicon layer. A plurality of contacts is formed through the interlevel dielectric layer to the CMOS transistor and the heterojunction bipolar transistor.

摘要翻译： 一种制造包括具有栅极结构的CMOS晶体管的BiCMOS集成电路的方法和具有外在基极结构的异质结双极晶体管。 提供衬底，并且在衬底上形成多晶硅层。 栅极结构和非本征基极结构形成在多晶硅层中。 多个触点通过层间介质层形成到CMOS晶体管和异质结双极晶体管。

公开(公告)号：US20050101096A1

公开(公告)日：2005-05-12

申请号：US10703284

申请日：2003-11-06

申请人： Jian Li ,  Lap Chan ,  Purakh Verma ,  Jia Zheng ,  Shao-Fu Chu

发明人： Jian Li ,  Lap Chan ,  Purakh Verma ,  Jia Zheng ,  Shao-Fu Chu

IPC分类号： H01L21/331 ,  H01L29/737 ,  H01L21/8222

CPC分类号： H01L29/66242 ,  H01L29/737

摘要： A method for manufacturing a lateral heterojunction bipolar transistor (HBT) is provided comprising a semiconductor substrate having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.

摘要翻译： 提供一种用于制造横向异质结双极晶体管（HBT）的方法，包括半导体衬底上的第一绝缘层的半导体衬底。 基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。 半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。 基底结构形成在基底沟槽中。 通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。 基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。