公开(公告)号：US06756634B2

公开(公告)日：2004-06-29

申请号：US09438310

申请日：1999-11-10

申请人： Mark A. Helm ,  Mark Fischer ,  John T. Moore ,  Scott Jeffrey DeBoer

发明人： Mark A. Helm ,  Mark Fischer ,  John T. Moore ,  Scott Jeffrey DeBoer

IPC分类号： H01L2992

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L29/511

摘要： In one aspect, the invention includes a method of forming a gated semiconductor assembly, comprising: a) forming a silicon nitride layer over and against a floating gate; and b) forming a control gate over the silicon nitride layer. In another aspect, the invention includes a method of forming a gated semiconductor assembly, comprising: a) forming a floating gate layer over a substrate; b) forming a silicon nitride layer over the floating gate layer, the silicon nitride layer comprising a first portion and a second portion elevationally displaced from the first portion, the first portion having a greater stoichiometric amount of silicon than the second portion; and c) forming a control gate over the silicon nitride layer. In yet another aspect, the invention includes a gated semiconductor assembly comprising: a) a substrate; b) a floating gate over the substrate; c) a control gate over the floating gate; and d) an electron barrier layer between the floating gate and the control gate, the electron barrier layer comprising a silicon nitride layer, the silicon nitride layer comprising a first portion and a second portion elevationally displaced from the first portion, the first portion having a greater stoichiometric amount of silicon than the second portion.

摘要翻译： 一方面，本发明包括一种形成门控半导体组件的方法，包括：a）在浮动栅极上形成氮化硅层; 以及b）在所述氮化硅层上形成控制栅极。 另一方面，本发明包括形成门控半导体组件的方法，包括：a）在衬底上形成浮栅; b）在所述浮栅上形成氮化硅层，所述氮化硅层包括从所述第一部分向前倾斜的第一部分和第二部分，所述第一部分具有比所述第二部分更大的化学计量的硅量; 以及c）在所述氮化硅层上形成控制栅极。 在另一方面，本发明包括门控半导体组件，其包括：a）衬底; b）衬底上的浮栅; c）浮动门上的控制门; 以及d）在所述浮动栅极和所述控制栅极之间的电子势垒层，所述电子势垒层包括氮化硅层，所述氮化硅层包括第一部分和从所述第一部分向上偏移的第二部分，所述第一部分具有 比第二部分更大的化学计量的硅。

公开(公告)号：US06265755B1

公开(公告)日：2001-07-24

申请号：US08557484

申请日：1995-11-14

申请人： Mamoru Shinohara

发明人： Mamoru Shinohara

IPC分类号： H01L2992

CPC分类号： H01L29/66189 ,  H01L27/0629 ,  H01L27/0805 ,  H01L28/40

摘要： A semiconductor integrated circuit having an MIS (metal-insulator silicon) capacitor. A first capacitor and a second capacitor are connected in series between a substrate terminal and the MIS capacitor. A power supply is connected between the first and second capacitors. This power supply controls the potential between the first and second capacitors to an arbitrary potential to prevent a digital signal transmitted to the substrate from entering to an external circuit connected with the MIS capacitor.

摘要翻译： 一种具有MIS（金属 - 绝缘体硅）电容器的半导体集成电路。 第一电容器和第二电容器串联连接在衬底端子和MIS电容器之间。 电源连接在第一和第二电容器之间。 该电源将第一和第二电容器之间的电位控制到任意电位，以防止传输到衬底的数字信号进入与MIS电容器连接的外部电路。

公开(公告)号：US06774453B2

公开(公告)日：2004-08-10

申请号：US10369551

申请日：2003-02-21

申请人： Akira Okita

发明人： Akira Okita

IPC分类号： H01L2992

CPC分类号： H01L27/14609 ,  H01L27/1463 ,  H01L27/14689 ,  H01L27/14812

摘要： Provided is a semiconductor device includes a semiconductor element having a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type which is formed in the first semiconductor region, an element isolation layer formed between the semiconductor element and an adjacent element, a third semiconductor region of the first conductivity type having a higher concentration than the first semiconductor region formed under the element isolation layer, and a conductor layer formed on a portion of the element isolation layer, in which a fourth semiconductor region of the first conductivity type having a higher concentration than the third semiconductor region is further provided in at least a portion of a region opposite to the conductor layer through the element isolation layer and wiched there between.

摘要翻译： 提供一种半导体器件，包括具有第一导电类型的第一半导体区域和形成在第一半导体区域中的第二导电类型的第二半导体区域的半导体元件，形成在半导体元件和相邻的半导体元件之间的元件隔离层 元件，具有比形成在元件隔离层下方的第一半导体区域更高的浓度的第一导电类型的第三半导体区域，以及形成在元件隔离层的一部分上的导体层，其中第一半导体区域的第四半导体区域 具有比第三半导体区域更高的浓度的导电类型还通过元件隔离层设置在与导体层相对的区域的至少一部分中，并且在其之间互相混合。

公开(公告)号：US06172378B2

公开(公告)日：2001-01-09

申请号：US09304457

申请日：1999-05-03

申请人： Christopher D. Hull ,  James Douglas Seefeldt ,  Kishore V. Seendripu

发明人： Christopher D. Hull ,  James Douglas Seefeldt ,  Kishore V. Seendripu

IPC分类号： H01L2992

CPC分类号： H01L29/94

摘要： Integrated circuit varactor structures that include either an P-gate/N-well or N-gate/P-well layer configuration formed on an SOI substrate. The varactor structure is completely electrically isolated from the substrate of the IC by an oxide layer of the SOI substrate and by oxide-filled trenches formed on both sides of the varactor structures. The isolation trenches preferably extend to the oxide layer of the SOI substrate. The P-gate/N-well varactor structure includes N+ implant regions formed in an N-well implant layer of the varactor. The N+ implant regions comprise the source and the drain of a varactor. A LOCOS layer may be formed over the N-well layer where the P-gate is formed over the LOCOS layer. The P-gate may be formed of polysilicon. The N-gate/P-well varactor structure includes P+ implant regions formed in a P-well implant layer of the varactor. The P+ implant regions comprise the source and the drain of a varactor. A LOCOS layer may be formed over the P-well layer where the N-gate is formed over the LOCOS layer. The N-gate may be formed of polysilicon. The P-gate/N-well varactor is ideally suited for use as a binary or digitally-controlled varactor because it abruptly changes from a first lower capacitance of C1 to a second higher capacitance of C2 as the D.C. control voltage is varied from a first to a second threshold level. In contrast, the N-gate/P-well varactor finds utility as an analog timing varactor of a fully integrated VCO device, for example, because it slowly changes from a first lower capacitance of C1 to a second higher capacitance of C2 as the D.C. control voltage is varied from low to high threshold voltage levels.

摘要翻译： 集成电路变容二极管结构，其包括形成在SOI衬底上的P栅极/ N阱或N栅极/ P阱层配置。 变容二极管结构通过SOI衬底的氧化物层和形成在变容二极管结构两侧的氧化物填充沟槽与IC的衬底完全电隔离。 隔离沟槽优选地延伸到SOI衬底的氧化物层。 P栅/ N阱变容二极管结构包括形成在变容二极管的N阱注入层中的N +注入区。 N +注入区域包括变容二极管的源极和漏极。 可以在N阱层上形成LOCOS层，其中P型栅极形成在LOCOS层上。 P栅可以由多晶硅形成。 N栅极/ P阱变容二极管结构包括形成在变容二极管的P阱注入层中的P +注入区域。 P +植入区域包括变容二极管的源极和漏极。 可以在LOCOS层上形成N栅极的P阱层上形成LOCOS层。 N栅极可以由多晶硅形成。 P栅极/ N阱变容二极管非常适合用作二进制或数字控制的变容二极管，因为随着直流控制电压从第一个电压变化而从C1的第一较低电容突然改变到第二较高的电容C2 达到第二阈值水平。 相比之下，N栅极/ P阱变容二极管可用作完全集成的VCO器件的模拟定时变容二极管，例如，因为它缓慢地从C1的第一较低电容变为C2的第二较高电容作为DC 控制电压从低到高阈值电压电平变化。

公开(公告)号：US06794700B1

公开(公告)日：2004-09-21

申请号：US10411522

申请日：2003-04-10

申请人： Eric Beach ,  Weidong Tian ,  Pinghai Hao

发明人： Eric Beach ,  Weidong Tian ,  Pinghai Hao

IPC分类号： H01L2992

CPC分类号： H01L28/40 ,  H01L21/31155 ,  H01L21/31629 ,  H01L27/0805

摘要： The present invention provides a capacitor 300, a method of manufacture therefor and an integrated circuit including the same. In one embodiment of the invention, the capacitor 300 includes a first conductive plate 320 located over a semiconductor substrate 310, wherein the first conductive plate 320 has a second conductive plate 340 located thereover. The capacitor 300, in the same embodiment, further includes a dielectric layer 330 located between the first conductive plate 320 and the second conductive plate 340, wherein the dielectric layer 330 includes a Group 17 element.

摘要翻译： 本发明提供一种电容器300及其制造方法和包括该电容器的集成电路。 在本发明的一个实施例中，电容器300包括位于半导体衬底310上方的第一导电板320，其中第一导电板320具有位于其上的第二导电板340。 在同一实施例中，电容器300还包括位于第一导电板320和第二导电板340之间的电介质层330，其中电介质层330包括第17族元件。

公开(公告)号：US06566220B2

公开(公告)日：2003-05-20

申请号：US10013234

申请日：2001-12-10

申请人： Manfred Engelhardt ,  Volker Weinrich ,  Franz Kreupl ,  Manuela Schiele

发明人： Manfred Engelhardt ,  Volker Weinrich ,  Franz Kreupl ,  Manuela Schiele

IPC分类号： H01L2992

CPC分类号： H01L28/75 ,  H01L27/10852 ,  H01L28/55

摘要： The invention relates to a method for fabricating a semiconductor memory component, in particular a DRAM or FeRAM having a silicon substrate. The lower electrode of a storage capacitor is insulated from the silicon substrate by a barrier layer. The barrier layer is patterned using a hard mask, in particular, made from SiO2, SiN, SiON, before the storage capacitor is applied, and the mask layer which remains after the patterning is removed so as to uncover the patterned barrier layer. The invention provides for the patterned barrier layer to be embedded in SiO2 by means of CVD (chemical vapor deposition) prior to the removal of the remaining mask layer, and for the remaining mask layer, together with the SiO2 embedding, to be removed from the surface of the barrier layer using an SiO2-CMP (chemical mechanical polishing) process.

公开(公告)号：US06552379B2

公开(公告)日：2003-04-22

申请号：US10121602

申请日：2002-04-15

申请人： Yukihiro Nagai

发明人： Yukihiro Nagai

IPC分类号： H01L2992

CPC分类号： H01L27/11502 ,  H01L27/10811 ,  H01L27/10852 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/60 ,  Y10S257/90

摘要： A semiconductor device with capacitors which have a structure wherein fluctuation in thickness does not occur, even in the case that a dielectric film of low coverage is used. The semiconductor device is provided with adjoining first and second capacitors, wherein the respective capacitor is provided with lower electrode, dielectric film which contacts the top surface of the lower electrode and which has peripheral sidewall surfaces that continue to the peripheral sidewall surfaces of the lower electrode, first upper electrode that contacts the top surface of the dielectric film and a second upper electrode that contacts the top surface of the first upper electrode and the semiconductor device is further provided with a partition insulating film which covers the sidewall surfaces of lower electrode and the dielectric layer between the capacitors so that the second upper electrode contacts the top surface of the partition insulating film.

公开(公告)号：US06342712B1

公开(公告)日：2002-01-29

申请号：US09341523

申请日：1999-08-13

申请人： Hiroshi Miki ,  Keiko Kushida ,  Yasuhiro Shimamoto ,  Shinichiro Takatani ,  Yoshihisa Fujisaki ,  Hiromi Nakai

发明人： Hiroshi Miki ,  Keiko Kushida ,  Yasuhiro Shimamoto ,  Shinichiro Takatani ,  Yoshihisa Fujisaki ,  Hiromi Nakai

IPC分类号： H01L2992

CPC分类号： H01L28/75 ,  H01L28/55 ,  H01L28/57 ,  H01L28/60

摘要： The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively act as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.

摘要翻译： 电容器的上电极由层叠膜构成，其用于防止氢原子到达电容器电极并降低性能。 在一个示例中，四层上电极分别用作肖特基势垒层，氢扩散防止层，反应防止层和吸附抑制层。 因此，可以防止由于还原气氛导致半导体器件中的电容下降，绝缘不良和电极剥离的发生。 另外，可以提高装置的长期可靠性。