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    METHOD FOR FABRICATING CONTACT STRUCTURE AND CONTACT STRUCTURE
    1.
    发明申请
    METHOD FOR FABRICATING CONTACT STRUCTURE AND CONTACT STRUCTURE 有权

    公开(公告)号：US20230138089A1

    公开(公告)日：2023-05-04

    申请号：US17867683

    申请日：2022-07-19

    申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

    发明人： Xin XIN ,  Jinghao WANG

    IPC分类号： H01L21/3213 ,  H01L21/3205 ,  H01L21/3215 ,  H01L27/108

    摘要： Embodiments provide a method for fabricating a contact structure and a contact structure. The method for fabricating a contact structure includes: providing a substrate, and sequentially arranging a first polysilicon layer and a first mask layer on a surface of the substrate; performing a first etching process on the first polysilicon layer and the first mask layer to form a stepped structure where a width of the first mask layer is smaller than a width of the first polysilicon layer; performing a second etching process on the substrate by using the first polysilicon layer as a mask to form a trench; depositing a second polysilicon layer in the trench, a top of the second polysilicon layer being not higher than a bottom of the first mask layer; and performing an annealing process to form the contact structure.

    HIGH ASPECT RATIO DIELECTRIC ETCH WITH CHLORINE
    2.
    发明申请
    HIGH ASPECT RATIO DIELECTRIC ETCH WITH CHLORINE 有权

    公开(公告)号：US20230127597A1

    公开(公告)日：2023-04-27

    申请号：US17907401

    申请日：2021-03-10

    申请人： Lam Research Corporation

    发明人： Rui Takahashi ,  Yilun Li ,  Eric A. Hudson ,  Youn-Jin Oh ,  Wonjae Lee ,  Leonid Belau ,  Andrew Clark Serino

    IPC分类号： H01L21/311 ,  H01L21/3213 ,  H01J37/32

    摘要： Various embodiments herein relate to methods and apparatus for etching recessed features on a semiconductor substrate. The techniques described herein can be used to form high quality recessed features with a substantially vertical profile, low bowing, low twisting, and highly circular features. These high quality results can be achieved with a high degree of selectivity and a relatively high etch rate. In various embodiments, etching involves exposing the substrate to plasma generated from a processing gas that includes a chlorine source, a carbon source, a hydrogen source, and a fluorine source. The chlorine source may have particular properties. In some cases, particular chlorine sources may be used. Etching typically occurs at low temperatures, for example at about 25C or lower.

    SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING SAME
    3.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATING SAME 有权

    公开(公告)号：US20230125245A1

    公开(公告)日：2023-04-27

    申请号：US17971632

    申请日：2022-10-23

    申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

    发明人： Gongyi WU ,  Xiaofei WU ,  Yachao XU

    IPC分类号： H01L21/223 ,  H01L27/108 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

    摘要： Embodiments discloses a semiconductor structure and a fabricating method. The method includes: forming a contact hole on a substrate; forming a first doped layer on a surface of the contact hole, and annealing the first doped layer; forming at least one second doped layer on the first doped layer, and annealing each of the at least one second doped layer; and forming a third doped layer on the at least one second doped layer to fill up the contact hole. A thickness of the at least one second doped layer is greater than a thickness of the third doped layer, and the thickness of the third doped layer is greater than the thickness of the first doped layer. Annealing not only can repair lattice mismatch and lattice defect in the first doped layer/second doped layer, but also can improve surface roughness of the first doped layer/second doped layer.

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230124829A1

    公开(公告)日：2023-04-20

    申请号：US18083894

    申请日：2022-12-19

    申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

    发明人： Fei ZHOU

    IPC分类号： H10B10/00 ,  H01L21/02 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L23/528

    摘要： Semiconductor device is provided. The semiconductor device includes a base substrate including a first region, a second region, and a third region, a first doped layer in the base substrate at the first region and a second doped layer in the base substrate at the third region, a first gate structure on the base substrate at the second region, a first dielectric layer on the base substrate, a first conductive layer on the first conductive layer and the second doped layer, a second conductive layer on a surface of the first conductive layer, and a third conductive layer on a contact region of the first gate structure. The second region is between the first region and the third region. The contact region is at a top of the first gate structure. A minimum distance between the second conductive layer and the third conductive layer is greater than zero.

    Methods For Non-Isothermal Wet Atomic Layer Etching
    6.
    发明申请
    Methods For Non-Isothermal Wet Atomic Layer Etching 有权

    公开(公告)号：US20230117790A1

    公开(公告)日：2023-04-20

    申请号：US17835065

    申请日：2022-06-08

    申请人： Tokyo Electron Limited

    发明人： Paul Abel

    IPC分类号： H01L21/3213 ,  H01L21/3105 ,  H01L21/02

    摘要： The present disclosure provides a non-isothermal wet atomic layer etch (ALE) process for etching polycrystalline materials, such as metals, metal oxides and silicon-based materials, formed on a substrate. More specifically, the present disclosure provides various embodiments of methods that utilize thermal cycling in a wet ALE process to independently optimize the reaction temperatures utilized within individual processing steps of the wet ALE process. Like conventional wet ALE processes, the wet ALE process described herein is a cyclic process that includes multiple cycles of surface modification and dissolution steps. Unlike conventional wet ALE processes, however, the wet ALE process described herein is a non-isothermal process that performs the surface modification and dissolution steps at different temperatures. This allows independent optimization of the surface modification and dissolution reactions.

    SELECTIVE SILICON DEPOSITION
    7.
    发明申请
    SELECTIVE SILICON DEPOSITION 有权

    公开(公告)号：US20230110474A1

    公开(公告)日：2023-04-13

    申请号：US17500664

    申请日：2021-10-13

    申请人： Applied Materials, Inc.

    发明人： Yifeng Zhou ,  Qian Fu

    IPC分类号： H01L21/3205 ,  H01L21/3213 ,  C23C16/24

    摘要： Exemplary semiconductor processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The substrate may include one or more patterned features separated by exposed regions of the substrate. The methods may include providing a hydrogen-containing precursor to the processing region of the semiconductor processing chamber. The methods may include forming a plasma of the silicon-containing precursor and the hydrogen-containing precursor. Forming the plasma of the silicon-containing precursor and the hydrogen-containing precursor may be performed at a plasma power of less than or about 1,000 W. The methods may include depositing a silicon-containing material on the one or more patterned features along the substrate. The silicon-containing material may be deposited on the patterned features at a rate of at least 2:1 relative to deposition on the exposed regions of the substrate.