公开(公告)号：US11626404B2

公开(公告)日：2023-04-11

申请号：US17216488

申请日：2021-03-29

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Ka-Hing Fung

IPC分类号： H01L29/165 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238

摘要： A semiconductor device includes a first channel region disposed over a substrate, a first source region and a first drain region disposed over the substrate and connected to the first channel region such that the first channel region is disposed between the first source region and the first drain region, a gate dielectric layer disposed on and wrapping the first channel region, a gate electrode layer disposed on the gate dielectric layer and wrapping the first channel region, and a second source region and a second drain region disposed over the substrate and below the first source region and the first drain region, respectively. The second source region and the second drain region are in contact with the gate dielectric layer. A lattice constant of the first source region and the first drain region is different from a lattice constant of the second source region and the second drain region.

公开(公告)号：US20230101723A1

公开(公告)日：2023-03-30

申请号：US18077142

申请日：2022-12-07

申请人： Intel Corporation

发明人： Andrew W. YEOH ,  Joseph STEIGERWALD ,  Jinhong SHIN ,  Vinay CHIKARMANE ,  Christopher P. AUTH

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11 ,  H01L49/02 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167

摘要： Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

公开(公告)号：US11610995B2

公开(公告)日：2023-03-21

申请号：US17941814

申请日：2022-09-09

申请人： Daedalus Prime LLC

发明人： Michael Jackson ,  Anand Murthy ,  Glenn Glass ,  Saurabh Morarka ,  Chandra Mohapatra

IPC分类号： H01L29/76 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L29/32 ,  H01L29/165

摘要： Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.

公开(公告)号：US20230082276A1

公开(公告)日：2023-03-16

申请号：US17988612

申请日：2022-11-16

申请人： Intel Corporation

发明人： Cory BOMBERGER ,  Anand MURTHY ,  Susmita GHOSE ,  Siddharth CHOUKSEY

IPC分类号： H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/32 ,  H01L29/165 ,  H01L29/167 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L29/06

摘要： Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, the fin including a defect modification layer on a first semiconductor layer, and a second semiconductor layer on the defect modification layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

公开(公告)号：US11600719B2

公开(公告)日：2023-03-07

申请号：US17706346

申请日：2022-03-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Zi-Ang Su ,  Ming-Shuan Li ,  Chih Chieh Yeh

IPC分类号： H01L29/737 ,  H01L29/73 ,  H01L29/06 ,  H01L29/167 ,  H01L29/10 ,  H01L29/165

摘要： The present disclosure provides embodiments of bipolar junction transistor (BJT) structures. A BJT according to the present disclosure includes a first epitaxial feature disposed over a well region, a second epitaxial feature disposed over the well region, a vertical stack of channel members each extending lengthwise between the first epitaxial feature and the second epitaxial feature, a gate structure wrapping around each of the vertical stack of channel members, a first electrode coupled to the well region, an emitter electrode disposed over and coupled to the first epitaxial feature, and a second electrode disposed over and coupled to the second epitaxial feature.

公开(公告)号：US20230066437A1

公开(公告)日：2023-03-02

申请号：US17525634

申请日：2021-11-12

申请人： GLOBALFOUNDRIES U.S. Inc.

发明人： Hong Yu ,  Judson R. Holt ,  Alexander Derrickson

IPC分类号： H01L29/735 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L29/10

摘要： The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base having at least one sidewall with a gradient concentration of semiconductor material; an emitter on a first side of the extrinsic base; and a collector on a second side of the extrinsic base.

公开(公告)号：US20230063301A1

公开(公告)日：2023-03-02

申请号：US17557176

申请日：2021-12-21

申请人： GLOBALFOUNDRIES U.S. Inc.

发明人： Alexander M. Derrickson ,  Arkadiusz Malinowski ,  Jagar Singh ,  Mankyu Yang ,  Judson R. Holt

IPC分类号： H01L29/737 ,  H01L29/165 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

摘要： The present disclosure relates to semiconductor structures and, more particularly, to annular bipolar transistors and methods of manufacture. The structure includes: a substate material; a collector region parallel to and above the substrate material; an intrinsic base region surrounding the collector region; an emitter region above the intrinsic base region; and an extrinsic base region contacting the intrinsic base region

公开(公告)号：US11594637B2

公开(公告)日：2023-02-28

申请号：US16833208

申请日：2020-03-27

申请人： Intel Corporation

发明人： Leonard P. Guler ,  Stephen Snyder ,  Biswajeet Guha ,  William Hsu ,  Urusa Alaan ,  Tahir Ghani ,  Michael K. Harper ,  Vivek Thirtha ,  Shu Zhou ,  Nitesh Kumar

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786 ,  H01L29/165 ,  H01L21/02 ,  H01L29/10

摘要： Gate-all-around integrated circuit structures having fin stack isolation, and methods of fabricating gate-all-around integrated circuit structures having fin stack isolation, are described. For example, an integrated circuit structure includes a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls. An isolation structure is on the top and along the sidewalls of the sub-fin structure. The isolation structure includes a first dielectric material surrounding regions of a second dielectric material. A vertical arrangement of horizontal nanowires is on a portion of the isolation structure on the top surface of the sub-fin structure.

公开(公告)号：US11587928B2

公开(公告)日：2023-02-21

申请号：US17093528

申请日：2020-11-09

申请人： Bell Semiconductor, LLC

发明人： Pierre Morin ,  Nicolas Loubet

IPC分类号： H01L27/092 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/165

摘要： Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

公开(公告)号：US20230049249A1

公开(公告)日：2023-02-16

申请号：US17978027

申请日：2022-10-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Kun-Mu LI ,  Tsz-Mei KWOK ,  Ming-Hua YU ,  Chan-Lon YANG

IPC分类号： H01L29/78 ,  H01L21/84 ,  H01L29/06 ,  H01L21/02 ,  H01L21/3115 ,  H01L27/12 ,  H01L29/66 ,  H01L29/165

摘要： A fin field effect transistor (Fin FET) device includes a fin structure extending in a first direction and protruding from an isolation insulating layer disposed over a substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.